DHM0800ALS1B datasheet, PDF - EEWORLD Datasheet

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DHM0800ALS1B: DescriptionMicroprocessor, 32-Bit, 800MHz, CMOS, CPGA453, CERAMIC, PGA-462; CategoryThe embedded processor and controller Microcontrollers and processors; File Size748KB，104 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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DHM0800ALS1B Overview

Microprocessor, 32-Bit, 800MHz, CMOS, CPGA453, CERAMIC, PGA-462

DHM0800ALS1B Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	PGA
package instruction	PGA, SPGA462,37X37
Contacts	462
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	13
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P453
low power mode	YES
Number of terminals	453
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	SPGA462,37X37
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.5,2.5 V
Certification status	Not Qualified
speed	800 MHz
Nominal supply voltage	1.5 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Preliminary Release

Mobile AMD Duron

Processor

Model 7 Data Sheet

Featuring:

Publication #

24068

Rev:

Issue Date:

December 2001

Preliminary Information

24068F—December 2001

Mobile AMD Duron™ Processor Model 7 Data Sheet

Contents

List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

Mobile AMD Duron™ Processor Model 7 Upgrades Versus

the Mobile AMD Duron Processor Model 3 . . . . . . . . . . . . . . . 2

Mobile AMD Duron Processor Model 7 Microarchitecture

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD Duron System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

2.4

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

FID_Change State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Processor Performance States and the FID_Change

Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 18

Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SYSCLK Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2

4.3

4.4

4.5

CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1

7.2

7.3

7.4

7.5

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Soft Voltage Identification (SOFTVID[4:0]) . . . . . . . . . . . . . 35

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 35

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 35

Table of Contents

iii

Preliminary Information

Mobile AMD Duron™ Processor Model 7 Data Sheet

24068F—December 2001

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Valid Voltage and Frequency Combinations . . . . . . . . . . . . . 36

VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . 37

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 40

SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 41

AMD Duron System Bus AC and DC Characteristics . . . . . . 43

General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 45

Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48

Reserved Pins DC Characteristics . . . . . . . . . . . . . . . . . . . . . 51

FID_Change Induced PLL Lock Time . . . . . . . . . . . . . . . . . . 52

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 53

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 56

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 56

Mobile AMD Duron Processor Model 7 and Northbridge

Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 61

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

AMD Duron System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

CLKIN and RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . 78

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78

CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 80

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 53

8.1

8.2

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.1

9.2

9.3

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.1

10.2

10.3

Table of Contents

Preliminary Information

24068F—December 2001

Mobile AMD Duron™ Processor Model 7 Data Sheet

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

RSVD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 81

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

SOFTVID[4:0] and VID[4:0] Pins. . . . . . . . . . . . . . . . . . . . . . . 81

STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . . . . 83

VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

VREF_SYS Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.1

Standard Mobile AMD Duron Processor Model 7

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . 87

Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Websites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table of Contents

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