CAT5401
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and SPI Interface
FEATURES
Four linear taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5 kΩ, 10 kΩ, 50 kΩ or
100 kΩ
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 100Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1 µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (W)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
NC
RL3
RH3
RW3
A0
SO
HOLD
SCK
RL2
RH2
SI
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
TSSOP Package (Y)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
R
H0
CS
SCK
SI
SO
R
H1
R
H2
R
H3
SPI BUS
INTERFACE
WIPER CONTROL
REGISTERS
R
W0
R
W1
WP
A
0
A
1
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
R
W2
R
W3
R
L0
R
L1
R
L2
R
L3
RW2
SCK
NC
HOLD
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-2012 Rev. J
CAT5401
PIN DESCRIPTIONS
Pin#
(SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin#
(TSSOP)
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
V
CC
R
L0
R
H0
R
W0
¯¯¯
CS
¯¯¯
WP
SI
A1
R
L1
R
H1
R
W1
GND
NC
R
W2
R
H2
R
L2
SCK
¯¯¯¯¯
HOLD
SO
A0
R
W3
R
H3
R
L3
NC
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for
Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
No Connect
Wiper Terminal for
Potentiometer 2
High Reference Terminal
for Potentiometer 2
Low Reference Terminal
for Potentiometer 2
Bus Serial Clock
Hold
Serial Data Output
Device Address, LSB
Wiper Terminal for
Potentiometer 3
High Reference Terminal
for Potentiometer 3
Low Reference Terminal
for Potentiometer 3
No Connect
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5401. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5401. During a read cycle,
data is shifted out on the falling edge of the serial
clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5401. Opcodes, byte
addresses or data present on the SI pin are latched on
the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in order
to initiate communication with the CAT5401.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
: Wiper
The four R
W
pins are equivalent to the wiper terminal of
a mechanical potentiometer.
¯¯¯: Chip Select
CS
¯¯¯ is the Chip select pin. ¯¯¯ low enables the
CS
CS
¯¯¯ high disables the CAT5401. ¯¯¯
CAT5401 and CS
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5401
draws ZERO current in the Standby mode. A high to
low transition on ¯¯¯ is required prior to any sequence
CS
being initiated. A low to high transition on ¯¯¯ after a
CS
valid write sequence is what initiates an internal write
cycle.
¯¯¯: Write Protect
WP
¯¯¯ is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
WP
¯¯¯ is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register
WP
is allowed). ¯¯¯ going low while ¯¯¯ is still low will interrupt a write to the registers. If the internal write cycle has
WP
CS
¯¯¯ going low will have no effect on any write operation.
already been initiated, WP
¯¯¯¯¯
HOLD: Hold
The ¯¯¯¯¯ pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without
HOLD
¯¯¯¯¯
having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be
¯¯¯¯¯
¯¯¯¯¯
ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any
¯¯¯¯¯
time this function is not being used.) HOLD may be tied high directly to V
CC
or tied to V
CC
through a resistor.
2
Doc. No. MD-2012 Rev. J
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5401
SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5401 to interface directly with
many of today's popular microcontrollers. The
CAT5041 contains an 8-bit instruction register. The
instruction set and the operation codes are detailed in
the instruction set table 3.
After the device is selected with ¯¯¯ going low the first
CS
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
DEVICE OPERATION
The CAT5401 is four resistor arrays integrated with
SPI serial interface logic, four 6-bit wiper control
registers and sixteen 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
).
R
H
and R
L
are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (R
W
) by a CMOS transistor switch. Only one
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the non-
volatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-2012 Rev. J
CAT5401
Absolute Maximum Ratings
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to V
SS(1) (2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25ºC)
Lead Soldering Temperature (10 s)
Wiper Current
Recommended Operating Conditions
Parameters
V
CC
Industrial Temperature
Potentiometer Characteristics
Over recommended operating conditions unless otherwise stated.
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(5)
Relative Linearity
(6)
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
Min
Typ
100
50
10
2.5
±20
25°C, each pot
I
W
= ±3 mA @ V
CC
= 3 V
I
W
= ±3 mA @ V
CC
= 5 V
V
SS
= 0 V
(4)
R
W
(n)(actual) - R(n)(expected)
R
W
(n+1) - [R
W
(n) + LSB]
(8)
(4)
(4)
(4)
R
POT
= 50 kΩ
(4)
(8)
Ratings
-55 to +125
-65 to +150
-2.0 to +V
CC
+ 2.0
-0.2 to +7.0
1.0
300
±12
Units
ºC
°C
V
V
W
ºC
mA
Ratings
+2.5 to +6
-40 to +85
Units
V
°C
Max
Units
kΩ
kΩ
kΩ
kΩ
%
%
mW
mA
Ω
Ω
V
nV
√
Hz
%
LSB
(7)
LSB
(7)
ppm/ºC
ppm/ºC
pF
MHz
I
W
R
W
R
W
V
TERM
VN
200
100
GND
0.4
1
50
+3
300
150
V
CC
+1
+0.2
+300
20
10/10/25
0.4
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(8) n = 0, 1, 2, ..., 63
Doc. No. MD-2012 Rev. J
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5401
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3 V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 2 MHz, SO = Open
Inputs = GND
V
IN
= GND or V
CC
, SO = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
µA
µA
µA
V
V
V
PIN Capacitance
(1)
Available over recommended operating range from T
A
= 25ºC, f = 1.0 MHz, V
CC
= 5 V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test
Output Capacitance (SO)
Input Capacitance (¯¯¯, SCK, SI, ¯¯¯, HOLD)
CS
WP ¯¯¯¯¯
Conditions
V
OUT
= 0V
V
IN
= 0V
Max.
8
6
Units
pF
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI
(
1)
t
FI(1)
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
Parameter
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
¯¯¯¯¯
HOLD to Output Low Z
Input Rise Time
Input Fall Time
¯¯¯¯¯
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
¯¯¯¯¯
HOLD to Output High Z
¯¯¯ High Time
CS
¯¯¯ Setup Time
CS
¯¯¯ Hold Time
CS
Test Conditions
Min
50
50
125
125
DC
Typ
Max
Units
ns
ns
ns
ns
3
50
2
2
MHz
ns
µs
µs
ns
ns
C
L
= 50 pF
100
100
10
250
0
250
100
250
250
250
ms
ns
ns
ns
ns
ns
ns
ns
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-2012 Rev. J
京公网安备 11010802033920号
EEWORLD
