FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver
August 2008
FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential
Receiver
Features
Greater than 400Mbs Data Rate
Power Supply Operation: 3.3V
Maximum Differential Pulse Skew: 0.4ns
Maximum Propagation Delay: 2.5ns
Low-Power Dissipation
Power-Off Protection
Fail-Safe Protection for Open-Circuit, Shorted, and
Terminated Conditions
Meets or Exceeds the TIA/EIA-644 LVDS Standard
Flow-through Pinout Simplifies PCB Layout
Description
This dual receiver is designed for high-speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The receiver translates LVDS
levels, with a typical differential input threshold of
100mV, to LVTTL signal levels. LVDS provides low EMI
at ultra-low power dissipation, even at high frequencies.
This device is ideal for high-speed transfer of clock and
data signals.
The FIN1028 can be paired with its companion driver,
the FIN1027, or any other LVDS driver.
Ordering Information
Part Number
FIN1028M
FIN1028MX
Operating
Temperature Range
-40 to +85°C
-40 to +85°C
Eco Status
RoHS
RoHS
Package
8-Lead Small Outline Package (SOIC)
JEDEC MS-012, 0.150 inch Narrow
8-Lead Small Outline Package (SOIC)
JEDEC MS-012, 0.150 inch Narrow
Packing
Method
Trays
Tape and Reel
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2001 Fairchild Semiconductor Corporation
FI1028 • Rev. 1.0.2
www.fairchildsemi.com
FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Reciever
Pin Configuration
Figure 1. SOIC Pin Assignments (Top View)
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
R
IN1-
R
IN1+
R
IN2+
R
IN2-
GND
R
OUT2
R
OUT1
V
CC
Description
Inverting LVDS Input
Non-Inverting LVDS Input
Non-Inverting LVDS Input
Inverting LVDS Input
Ground
LVTTL Data Output
LVTTL Data Output
Power Supply
Function Table
Inputs
R
IN+
LOW
HIGH
Fail-Safe Conditions
Note:
1. Fail-safe=open, shorted, terminated.
(1)
Outputs
R
IN-
HIGH
LOW
R
OUT
LOW
HIGH
HIGH
© 2001 Fairchild Semiconductor Corporation
FIN1028 • Rev. 1.0.2
www.fairchildsemi.com
2
FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Reciever
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
V
CC
R
INx+
, R
INx-
R
OUTx
I
O
T
STG
T
J
T
L
ESD
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Output Current
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering 10 Seconds
Human Body Model, JESD22-A114
Machine Model, JESD22-A115
Min.
-0.5
-0.5
-0.5
-65
Max.
4.6
4.7
6.0
16
+150
+150
+260
≥6500
≥300
Unit
V
V
V
mA
°C
°C
°C
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
⏐V
ID
⏐
V
IC
T
A
Input Voltage
Parameter
Supply Voltage
Magnitude of Differential Voltage
Common-Mode Input Voltage
Operating Temperature
Min.
3.0
0
100
0.05
-40
Max.
3.6
V
CC
V
CC
2.35
+85
Unit
V
V
mV
V
°C
© 2001 Fairchild Semiconductor Corporation
FIN1028 • Rev. 1.0.2
www.fairchildsemi.com
3
FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Reciever
DC Electrical Characteristics
Typical values are at T
A
=25°C and with V
CC
=3.3V. Over-supply voltage and operating temperature ranges, unless
otherwise noted.
Symbol
V
TH
V
TL
I
IN
I
I(OFF)
V
OH
V
OL
V
IK
I
CC
C
IN
C
OUT
Parameter
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Current
Power-off Input Current
Output HIGH Voltage
Output LOW Voltage
Input Clamp Voltage
Power Supply Current
Input Capacitance
Output Capacitance
Conditions
Figure 2, Table 1
Figure 2, Table 1
V
IN
=0V or V
CC
V
CC
=0V, V
IN
=0V or 3.6V
I
OH
=-100µA
I
OH
=-8mA
I
OL
=100µA
I
OL
=8mA
I
IK
=-18mA
R
IN+
=1V and R
IN-
=1.4V or
R
IN+
=1.4V and R
IN-
=1V
Min.
-100
Typ.
Max.
100
±20
±20
Units
mV
mV
µA
µA
V
V
CC
-0.2
2.4
0.2
0.5
-1.5
9
4
6
V
V
mA
pF
pF
DC Electrical Characteristics
Typical values are at T
A
=25°C and with V
CC
=3.3V. Over-supply voltage and operating temperature ranges, unless
otherwise noted.
Symbol
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(LH),
t
SK(HL)
t
SK(PP)
Parameter
Differential Propagation Delay,
LOW-to-HIGH
Differential Propagation Delay,
HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew
⏐t
PLH -
t
PHL
⏐
Channel-to-Channel Skew
Part-to-Part Skew
(3)
(2)
Conditions
Min.
0.9
0.9
Typ.
Max.
2.5
2.5
Units
ns
ns
ns
ns
⏐V
ID
⏐=400mV,
C
L
=10pF
Figure 2, Figure 3
0.5
0.5
0.4
0.3
1.0
ns
ns
ns
Notes:
2. t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and
are switching in the same direction.
3. t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two
devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with
the same supply voltage, same temperature, and have identical test circuits.
© 2001 Fairchild Semiconductor Corporation
FIN1028 • Rev. 1.0.2
www.fairchildsemi.com
4
FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver
Figure 2. Differential Driver Propagation Delay and Transition Time Test Circuit
Notes:
4. C
L
includes all probe and fixture capacitances.
5. All input pulses have frequency = 10MHz, t
R
or t
F
=1ns.
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
V
IA
V
IB
Resulting Differential
Input Voltage (mV)
V
ID
Resulting Common
Mode Input Voltage (V)
V
IC
1.25
1.15
2.4
2.3
0.1
0
1.5
0.9
2.4
1.8
0.6
0
1.15
1.25
2.3
2.4
0
0.1
0.9
1.5
1.8
2.4
0
0.6
100
-100
100
-100
100
-100
600
-600
600
-600
600
-600
1.2
1.2
2.35
2.35
0.05
0.05
1.2
1.2
2.1
2.1
0.3
0.3
Figure 3. AC Waveforms
© 2001 Fairchild Semiconductor Corporation
FIN1028 • Rev. 1.0.2
www.fairchildsemi.com
5
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