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A42MX24-PL84X79

Description
Field Programmable Gate Array, 912 CLBs, 36000 Gates, CMOS, PQCC84, PLASTIC, LCC-84
CategoryProgrammable logic devices    Programmable logic   
File Size3MB,124 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
Download Datasheet Parametric View All

A42MX24-PL84X79 Overview

Field Programmable Gate Array, 912 CLBs, 36000 Gates, CMOS, PQCC84, PLASTIC, LCC-84

A42MX24-PL84X79 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrosemi
package instructionQCCJ,
Reach Compliance Codecompliant
Other featuresALSO OPERATE AT 5.0V SUPPLY
Combined latency of CLB-Max2.5 ns
JESD-30 codeS-PQCC-J84
JESD-609 codee3
length29.3116 mm
Humidity sensitivity level3
Configurable number of logic blocks912
Equivalent number of gates36000
Number of terminals84
Maximum operating temperature70 °C
Minimum operating temperature
organize912 CLBS, 36000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)245
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width29.3116 mm
v6.1
40MX and 42MX FPGA Families
Features
High Capacity
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
HiRel Features
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
High Performance
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
Product Profile
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
User I/O (maximum)
PCI
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
A40MX02
3,000
295
9.5 ns
147
1
57
44, 68
100
80
A40MX04
6,000
547
9.5 ns
273
1
69
44, 68, 84
100
80
A42MX09
14,000
348
336
5.6 ns
348
516
2
104
84
100, 160
100
176
A42MX16
24,000
624
608
6.1 ns
624
928
2
140
84
100, 160, 208
100
176
A42MX24
36,000
954
912
24
6.1 ns
954
1,410
2
176
Yes
Yes
84
160, 208
176
A42MX36
54,000
2,560
1,230
1,184
24
6.3 ns
10
1,230
1,822
6
202
Yes
Yes
208, 240
208, 256
272
April 2009
© 2009 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
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