32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Advance Information
FEATURES:
• Flash Organization:
– 2M x 16
• PSRAM Organization:
– 8 Mbit: 512k X 16
– 16 Mbit: 1M x 16
• Single Voltage Read and Write Operations
–
V
DD
= 1.7V - 1.95V for Program, Erase and Read
• Top or Bottom Boot Block Protection
– Bottom Boot Protection - SST34WA32x3
– Top Boot Protection - SST34WA32x4
• Multiplexed Data/Address for reduced I/O count
– A
15
–A
0
multiplexed as DQ
15
–DQ
0
– Addresses are latched by AVD# control input when
BEF# is low
• Low Power Consumption (Typical)
– Standby Current: 50 µA
• Flexible Flash Memory Organization
– 4 Banks (512 KW)
– 63 Uniform 32 KWord blocks
– Uniform Sectors (2KWord) for entire memory array
• Concurrent Flash Memory Operation
– Read While Program (RWP)
– Read While Erase (RWE)
• Erase-Suspend/Erase-Resume Capability
– Read while Erase-Suspend
– Program while Erase-Suspend
– Read while Program during Erase-Suspend
• Industry Standard CFI interface compatible
•
Flash Synchronous Burst Mode Read (54 MHz/66 MHz)
– Continuous, Sequential Linear Burst
– 8/16/32-words with Wrap-Around Burst
– 8/16/32-words without Wrap-Around Burst
– Burst Access Time: 13.5 ns/11.5 ns
– Asynchronous Random Address Access: 70 ns
PSRAM Burst Mode Read/Write Access (54 MHz/66 MHz)
– Continuous, Sequential Linear Burst
– 4/8/16-words with Wrap-Around Burst
– 4/8/16-words without Wrap-Around Burst
– Burst Access Time: 13.5 ns/11.5 ns
– Asynchronous Random Address Access: 70 ns
Fast Program and Erase (Typical)
– Word Program Time: 10 µs
– Sector/Block Erase Time: 15 ms
– Chip Erase Time: 30 ms
Expanded Block Locking
– All blocks locked at Power-up
– Any block can be locked/unlocked by software
Flash Security ID
– 128-bit unique ID – factory preset
– 128-word non-erasable, lockable User-programmed
ID bits (“OTP-like”)
End-of-Write Detection
– Data# Polling
– Toggle bit
Packages Available
– 56-ball VFBGA (6 x 8mm)
Superior Reliability
– Endurance per sector: 1,000,000 cycles (typical)
– Greater than 100 years Data Retention
All non-Pb (lead-free) devices are RoHS compliant
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PRODUCT DESCRIPTION
The SST34WA32A3 / SST34WA32A4 / SST34WA3283 /
SST34WA3284 are 32 Mbit (2 Mbit x16) ComboMemory
devices which integrate a 32 Mbit flash with either a 16 Mbit
PSRAM or 8 Mbit PSRAM in a multi-chip package (MCP).
These devices utilize a single 1.8V supply and support
burst mode access and address / data multiplex
architecture.
The Combo Memory devices feature a 512 KWord uniform
multi-bank flash memory architecture that consists of four
banks that contain individually-erasable blocks and sectors
for increased flexibility. Either the top or bottom bank,
consists of 15 standard 32 KWord blocks and four
parameter 8 KWord blocks for added granularity. The
remaining three banks each contain uniform 32 KWord
blocks. Each 32 KWord block is further divided into sixteen
uniform 2 KWord sectors. Any bank can be read while
another bank is being erased or programmed, with zero
latency. In addition, these devices provide Erase-Suspend
mode during which data can be programmed to, or read
from, any sector or block that is not being erased.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
1
SST34WA32A3/32A4/3283/3284 support synchronous
Burst mode Read from any address location of the flash
memory array; and Burst mode Read and Write from any
address location of the PSRAM. The Burst modes allow
the devices to Read or Write sequential data with
significantly shorter latency delays than during a random
read or write.
To protect against inadvertent write, the flash memory bank
offers an expanded Block Locking scheme. Each block can
be individually locked, and the top or bottom 8 KWord
parameter blocks of each boot block can be individually
locked for finer granularity. In addition, a 136-words Security
ID, included on the flash memory, increases system design
security.
Designed, manufactured, and tested for applications
requiring low power and small form factor the
SST34WA32A3/32A4/3283/3284 are offered in an
extended temperature with a small footprint package to
meet board space constraints requirement. See Figure 8
for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Advance Information
DEVICE OPERATION
The SST34WA32A3/32A4/3283/3284 control operation of
either the flash or the PSRAM memory bank using BEF#
and BES#.
When BEF# is low, the flash bank is activated for Read,
Program, or Erase operation. When BES# is low, the
PSRAM is activated for Read and Write operation.
Do not assert BEF# and BES# low at the same time. If all
bank enable signals are asserted, bus contention will result
and the device may suffer permanent damage.
Concurrent Read/Write Operation
The multi-bank architecture of the flash memory of this
device allows zero latency Concurrent Read/Write
operation whereby the user can read from one bank of the
flash while programming or erasing in another bank. With
this operation a user can read system code in one bank
while updating data in another bank. A unique feature of
the SST34WA32A3/32A4/3283/3284 is ability to Read
during an Erase-Suspend even while Programming in
another bank. This feature is designed to respond to
interrupt requests during concurrent operation. See Table
2, Current Read/Write State.
TABLE 2: Concurrent Read/Write State
Current Operation in One
Bank
Read
Read
Write
Write
No Operation
No Operation
Possible Operation in Any
Other Bank
No Operation
Write
Read
No Operation
Read
Write
T2.0 1358
Flash Memory
Various commands are used to initiate the memory
operation functions of the device. Commands are written to
the device using standard microprocessor write
sequences. See Table 20 on page 30 for the command
sequence for each function.
The flash memory of SST34WA32A3/32A4/3283/3284 has
an Auto Low Power mode which puts the device in a “near
stand-by” mode after data has been accessed with a valid
Read operation. This reduces the flash active read current.
The Auto Low Power mode reduces the current
consumption of the flash memory to stand-by level. The
flash memory exits the Auto Low Power mode with any
address or flash control signal transition; therefore, there is
no access time penalty for Read cycles.
.
Note:
For the purposes of this table, “Write” means to perform Sec-
tor/Block or Word-Program operations as applicable to the
appropriate bank.
TABLE 1: Critical Parameters
Critical Parameters
Values Units
70
13.5
11.5
ns
ns
ns
T1.0 1358
Max Random Address Access Time
Max Synchronous Access Time (54 MHz)
Max Synchronous Access Time (66 MHz)
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
2
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Advance Information
Asynchronous Read
The default configuration of the flash memory on power-up,
or after a hardware reset via the RST# pin, is
Asynchronous Read. To read data from the flash memory
array, the system must assert a valid address on A/DQ
15
–
A/DQ
0
and A
20
–A
16
, while AVD# and BEF# are at
V
IL
.
During the read, WE# remains at V
IH
and CLK is X for
Asynchronous Read, the rising edge of AVD# latches the
address, and OE# is driven to V
IL
. The data appears on A/
DQ
15
–A/DQ
0.
For details, see Figure 9. Since the memory
array is divided into four banks, each bank remains enabled
for read access until the command register contents are
altered.
Address access time (T
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (T
CE
) is the delay from the stable addresses
and stable BEF# to valid data at the outputs. The output
enable access time (T
OE
) is the delay from the falling edge
of OE# to valid data at the output.
The internal state machine is set to read array data upon
device power-up or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition.
Burst Mode Read (Synchronous)
The SST34WA32A3/32A4/3283/3284 flash memory
default configuration on power-up or after reset is
Asynchronous Read. However, it can be configured to
operate in a Synchronous Read mode with a continuous,
sequential linear burst operation or a linear burst operation
of 8-, 16-, or 32-words length with wrap-around.
Before setting the flash memory configuration to Burst
Mode, determine the number of wait states for the initial
word access time (T
IACC
) and the desired Burst mode—
continuous with, or without, wrap-around.
WAIT States
On power up, the flash memory of SST34WA32A3/32A4/
3283/3284 defaults to asynchronous read operation. The
device is automatically enabled for burst mode on the first
rising edge on the CLK input, while the AVD# is held low
and the addresses are latched on the first rising edge of the
CLK. Prior to activating the clock signal, the system
determines how many wait states are desired for the initial
word (T
IACC
) of each burst session. The system then writes
the Set Configuration Register command sequence.
The device automatically delays RY/BY# by the needed
number of clock cycles if data is not ready. Refer to the
details in “Handshaking Feature” section.
The initial word is output on the Data Bus T
IACC
after the
active edge of the first CLK cycle. Each successive clock
cycle automatically increments the addresses counter.
Subsequent words are output on the Data Bus T
BACC
after
the active edge of each successive clock cycle.
To return the device to Asynchronous Read mode, either
drive BEF# to
V
IH
or drive RST# to
V
IL
.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Active CLK edge
when AVD# is low
BEF# VIH
RST# VIL
Synchronous Read
Mode Only
1358 F01.0
FIGURE 1: Synchronous/Asynchronous State Diagram
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
3
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Advance Information
8-, 16-, 32-Words Linear Burst Mode with Wrap-
Around
The flash memory of the SST34WA32A3/32A4/3283/3284
device supports a synchronous read operation with a
Linear Burst mode of a pre-determined word length with
wrap-around. Groups of 8, 16, and 32 words can be read in
this way as defined in Table 3.
In 8, 16, and 32-words Linear Burst mode operation, the
starting address of the linear burst sequence is the address
written to the device. Each successive clock cycle
automatically increments the address counter until the top
address of the group is reached. Once the top address is
reached, the address wraps back to the first address of the
selected group and continues incrementing from there.
An example of an 8-word linear Burst mode with Wrap-
Around is as follows: if the starting address in the 8-word
mode is 11H (8 words group start = 10H, group end =
17H), the address range to be read would be 10H-17H,
and the burst sequence would be 11H -12H -13H - 14H -
15H - 16H - 17H - 10H - and so on.
The RY/BY# pin will indicate when valid data is present on
the data bus.
TABLE 3: 8-, 16-, 32-Words Linear Burst Mode Wrap-Around Groups
Group Size
Address Ranges
8 words
16 words
32 words
00000H - 00007H
00000H - 0000FH
00000H - 0001FH
00008H - 0000FH
00010H - 0001FH
00020H - 0003FH
00010H - 00017H
00020H - 0002FH
00040H - 0005FH
…
…
…
(A)
1
- (A + 7H)
(B)
1
- (B + FH)
(C)
1
- (C + 1FH)
T3.0 1358
1. A is a multiple of 00008H, B is a multiple of 00010H, and C is a multiple of 00020H.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
4
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Advance Information
8-16-32-Words Linear Burst Mode without Wrap-
Around
The SST34WA32A3/32A4/3283/3284 flash memory
supports a synchronous read operation with a Linear Burst
mode that does not wrap around. A fixed number of words
predefined as 8-, 16-, or 32-words are read from
consecutive addresses starting with the initial word, which
is written to the device. Once the fixed number of words are
read completely, the Burst Read operation stops and the
RY/BY# output goes low. There is no group limitation as
there is with Linear Burst with Wrap-Around. See Table 3
for group definitions.
An example of an 8-word linear Burst mode without Wrap-
Around is as follows: for an 8-word length Burst Read, if the
starting address written to the device is 39h, the burst
sequence would be 39-3A-3B-3C-3D-3E-3F-40h, and the
read operation will be terminated at 40h. In a similar
fashion, the 16-word and 32-word modes begin their burst
sequence on the starting address written to the device, and
Continuously Read to the predefined word length, of 16 or
32 words.
The operation is similar to the Continuous Burst, but will
stop the operation at fixed word length. If the device
crosses the first 32-word address boundary during burst
read, a latency may occur before data appears for the next
address and RY/BY# is pulsing low. If the burst read start
address is 8-word boundary aligned (A0 = A1 = A2 = 0),
the latency does not occur. If the host system crosses the
bank boundary, the device will react in the same manner as
in the Continuous Burst.
Continuous Linear Burst Mode
The flash memory of SST34WA32A3/32A4/3283/3284
supports a synchronous read operation with a continuous,
sequential linear Burst mode read. When in this mode, the
Addresses are automatically incremented linearly with
every successive clock active edge. If the device reaches
the Highest Memory Location Address (FFFFFH), it will
continue the continuous, sequential linear Burst read
operation by wrapping around to Address 00000H. The
Burst operation will continue sequentially until another
address is latched via the AVD# pin, until BEF# is driven to
V
IH
, or until RST# is driven to
V
IL
.
When an address is latched via AVD# pin with active edge
of CLK, a new burst read will start with a new initial
address.
If the continuous, sequential linear burst read sequence
crosses a bank boundary into a bank that is performing a
Programming or Erasing operation, the device will provide
status information. Once the system has completed the
status read operation, or the device has completed the
Program/Erase Operation, the system is allowed to start a
new burst read operation. In this case a new address
needs to be latched via the AVD# pin.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
In synchronous, continuous, sequential, linear read array, a
latency in output data may occur when a burst sequence
crosses the first 32-word address boundary. If the burst
read start address is 8-word boundary aligned (A
0
= A
1
=
A
2
= 0), the delay does not occur. If the burst read start
address is mis-aligned to an 8-word boundary, the delay
occurs once per burst-mode read sequence. The RY/BY#
signal will indicate this delay to the system.
Burst Register
The flash memory of SST34WA32A3/32A4/3283/3284
defaults to Asynchronous Read on power-up. However, it
can be configured to operate in a Synchronous Read
Mode with continuous, sequential linear burst operation
and linear burst operation of 8-, 16-, 32- words length with
wrap-around.
The Burst Register is used to configure the type of read bus
access the flash memory will perform by setting the desired
Mode of Burst (continuous or wrap-around) and the
number of wait states for the initial word access time
(T
IACC
).
The user can set the Burst Register with the Set Burst
Register Command. The Burst Register will retain its
information until it is reset via the RST# pin or after Power-
Up.
The Set Burst Register Command is initiated by executing
a three-cycle command sequence. On the last bus cycle,
Data is C0H, address bits A
11
–A
0
are 555H, and address
bits A
17
–A
12
set the code to be latched, as shown in
Table 4.
Upon power-up or hardware reset using the RST# pin, the
device will be in the default state. The Burst Register
cannot be changed if the device is Programming, Erasing,
or if it is in Sector Lock/Unlock mode.
5
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