White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
EDI4164MEV-RP
WRITE CYCLE, EARLY AND DELAYED WRITE
(VCC=3.3V±0.3V)Notes1,2,5
50ns
Parameter
CAS Setup for CAS before RAS Refresh
CAS Hold for CAS before RAS Refresh
Precharge to CAS Active
Access Time from CAS Precharge
EDO Page Cycle Time
EDO Page Read-Modify-Write Cycle Time
CAS precharge time (EDO cycle)
RAS pulse width (EDO Cycle)
Output Disable Time after OE High
Write Low to Next OE Low
OE Low to CAS High Setup Time
OE High Hold From CAS High
OE High Pulse Width
OE Setup prior to RAS during
Hidden Refresh Cycle
OE delay from WE
WE pulse to disable at CAS high
Symbol
t
CSR
t
CHR
t
RPC
t
CPA
t
PC
t
PRWC
t
CP
t
RASP
t
OD
t
OEH
t
OES
t
OEHC
t
OEP
t
ORD
t
WHZ
t
WPZ
Min
5
10
5
20
47
8
50
0
8
4
5
7
0
0
10
Max
Min
5
10
5
25
56
10
60
0
10
5
10
10
0
0
10
60ns
Max
Min
5
15
5
30
71
10
70
0
12
5
10
10
0
0
10
70ns
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
28
35
40
3
125K
13
125K
15
125K
20
6
10
13
15
NOTES:
1. An initial pause of 200µs is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved, and must be repeated
whenever t
REF
is exceeded.
2. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
(min) and V
IL
(max) and are
assumed to be 3ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
5. Assumes that t
RCD
≥
t
RCD
(max)
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
or V
OL
.
7. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If t
WCS
≥
t
WCS
(min), the
cycle is an early write and the data output will remain high impedance for the duration of the cycle. If t
CWD
≥
t
CWD
(min), t
RWD
> t
RWD
(min) and t
AWD
> t
AWD
(min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is
satisfied, the condition of the data out is indeterminate.
8. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in early write cycles and to the WE falling edge in OE controlled write cycle and read-modify-write
cycles.
10.Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by t
AA
.
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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