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IDT7027S35PF9

Description
Dual-Port SRAM, 32KX16, 35ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size182KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7027S35PF9 Overview

Dual-Port SRAM, 32KX16, 35ns, CMOS, PQFP100, TQFP-100

IDT7027S35PF9 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionTQFP-100
Contacts100
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN; LOW POWER STANDBY MODE
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX16
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
Low-power operation
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for bus
matching capability.
Dual chip enables allow for depth expansion without
external logic
IDT7027S/L
IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
CE
0L
CE
1L
OE
L
LB
L
R/
W
R
UB
R
CE
0R
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
A
14L
A
0L
32Kx16
MEMORY
ARRAY
7027
I/O
Control
I/O
Control
I/O
8-15R
I/O
0-7R
BUSY
R
A
14R
A
0R
(1,2)
.
Address
Decoder
A
14L
A
0L
CE
0L
CE
1L
OE
L
R/W
L
Address
Decoder
A
14R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
0R
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3199 drw 01
SEM
L
INT
L
(2)
M/S
(2)
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JULY 2004
DSC 3199/8
1
©2004 Integrated Device Technology, Inc.
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