NB7L14
2.5V / 3.3V 7GHz/10Gbps
Differential 1:4 LVPECL
Fanout Buffer
Multi−Level Inputs w/ Internal
Termination
Description
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MARKING
DIAGRAM*
16
QFN−16
MN SUFFIX
CASE 485G
1
NB7L
14
ALYWG
G
16
1
QFN−16
MN SUFFIX
CASE 485AE
7L14
ALYWG
G
The NB7L14 is a differential 1:4 LVPECL fanout buffer. The
NB7L14 produces four identical LVPECL output copies of Clock or
Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the
NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock or Data distribution applications.
The differential inputs incorporate internal 50
W
termination
resistors that are accessed through the VT Pin. This feature allows the
NB7L14 to accept various logic standards, such as LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels. The V
REFAC
reference
output can be used to rebias capacitor−coupled differential or
single−ended input signals. The 1:4 fanout design was optimized for
low output skew applications.
The NB7L14 is a member of the GigaComm™ family of high
performance clock products.
Features
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Data Rate > 10.7 Gb/s
Input Clock Frequency > 7 GHz
165 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
<15 ps max Output Skew
<0.8 ps maximum RMS Clock Jitter
<15 ps pp of Data Dependent Jitter
Differential LVPECL Outputs, 720 mV peak−to−peak, typical
LVPECL Operating Range: V
CC
= 2.375 V to 3.6 V with GND = 0 V
NECL Operating Range: V
CC
= 0 V with GND = −2.375 V to −3.6 V
Internal Input Termination Resistors, 50
W
V
REFAC
Reference Output
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
•
−40°C to +85°C Ambient Operating Temperature
•
These are Pb−Free Devices
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
50
W
VT
50
W
IN
V
REFAC
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
July, 2015 − Rev. 6
Publication Order Number:
NB7L14/D
NB7L14
GND Q0
16
IN
VT
V
REFAC
IN
15
Q0
14
V
CC
Exposed Pad (EP)
13
1
2
NB7L14
3
4
12 Q1
11 Q1
10 Q2
9
Q2
5
GND
6
Q3
7
Q3
8
V
CC
Figure 2. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
Name
IN
I/O
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
−
Description
Non−inverted Differential Input. Note 1. Internal 50
W
Resistor to Termination Pin, VT
2
3
4
VT
VREFAC
IN
Internal 50−W Termination Pin for IN/IN inputs.
Output Reference Voltage for capacitor−coupled inputs
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
−
LVPECL Output
LVPECL Output
−
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
−
LVPECL Output
LVPECL Output
−
−
Inverted Differential Input. Note 1. Internal 50
W
Resistor to Termination Pin, VT.
5
6
7
8
9
10
11
12
13
14
15
16
−
GND
Q3
Q3
VCC
Q2
Q2
Q1
Q1
VCC
Q0
Q0
GND
EP
Negative Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Negative Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for im-
proved heat transfer out of package. The exposed pad must be attached to a heat−sinking con-
duit. The pad is electrically connected to the die, and must be electrically connected to device
GND.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN input, then, the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7L14
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN−16
Oxygen Index: 28 to 34
Value
> 2000 V
> 150 V
Level 1
UL 94 V−0 @ 0.125 in
173
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
IO
V
INPP
I
IN
I
OUT
I
VFREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input/Output Voltage
Differential Input Voltage |D − D|
Input Current Through R
T
(50
W
Resistor)
Output Current (LVPECL Output)
V
REFAC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case) (Note 4)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
QFN−16
QFN−16
QFN−16
QFN−16
Continuous
Surge
Condition 1
GND = 0 V
GND = 0 V
−0.5
v
V
Io
v
V
CC
+ 0.5
Condition 2
Rating
−0.5 V to +4.0
4.0
2.8
"40
50
100
"1.5
−40 to +85
−65 to +150
42
35
4
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L14
Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS
V
CC
= 2.375 V to 3.6V, GND = 0 V, T
A
= −40°C to +85°C
Symbol
POWER SUPPLY CURRENT
V
CC
I
CC
Power Supply Voltage
Power Supply Current (Inputs and Outputs Open)
V
CC
= 2.5 V
V
CC
= 3.3 V
2.375
3.0
2.5
3.3
85
2.625
3.6
105
V
mA
Characteristic
Min
Typ
Max
Unit
LVPECL OUTPUTS
(Notes 5 & 6)
V
OH
Output HIGH Voltage
V
CC
= 2.5V
V
CC
= 3.3V
V
OL
Output LOW Voltage
V
CC
= 2.5 V
V
CC
= 3.3 V
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(see Figure 5 & 7) (Note 7)
V
IH
V
IL
V
th
V
ISE
VREFAC
V
REFAC
Output Reference Voltage (100
mA
Load)
V
CC
− 1400
V
CC
− 1300
V
CC
− 1000
mV
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage Amplitude (V
IH
− V
IL
)
V
th
+ 75
GND
1125
150
V
CC
V
th
− 75
V
CC
− 75
2800
mV
mV
mV
mV
V
CC
– 1145
1355
2155
V
CC
– 2000
500
1300
V
CC
– 900
1600
2400
V
CC
– 1700
800
1600
V
CC
– 825
1675
2475
V
CC
– 1500
1000
1800
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figure 6 & 8) (Note 9)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
− V
ILD
)
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
Input HIGH Current IN / IN, (VT Open)
Input LOW Current IN / IN, (VT Open)
1200
0
100
950
−150
−150
V
CC
V
IHD
− 50
2800
V
CC
− 50
150
150
mV
mV
mV
mV
mA
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVPECL outputs loaded with 50
W
to V
CC
− 2.0 V for proper operation.
6. Input and output parameters vary 1:1 with V
CC
.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
MR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
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NB7L14
Table 5. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C ; (Note 11)
Symbol
f
MAX
f
DATAMAX
V
OUTPP
t
PLH
,
t
PHL
t
SKEW
Characteristic
Maximum Input Clock Frequency; V
OUT
w
400 mV
Maximum Operating Data Rate; NRZ, (PRBS23)
Output Voltage Amplitude (Note 15)
(See Figure 9)
Propagation Delay IN to Q
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
RMS Random Clock Jitter (Note 13)
Peak−to−Peak Data Dependent Jitter (Note 14)
f
in
v
7 GHz
f
in
v
7 GHz
f
in
v
10.7 Gb/s
45
f
in
v
5 GHz
f
in
≤
7 GHz
Min
7
10
500
400
125
Typ
8
11
720
450
165
200
15
15
50
55
Max
Unit
GHz
Gbps
mV
ps
ps
3
50
t
DC
t
JITTER
%
ps rms
ps pk−pk
fs
0.5
5
24
100
0.8
15
t
jit(f)
V
INPP
t
r
t
f
Additive RMS Phase Jitter
f
c
= 622.08 MHz, Integration Range: 12 kHz to 20 MHz (See Figure 17)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
Output Rise/Fall Times @ 1.0 GHz
(20% − 80%)
Qx, Qx
1200
45
60
mV
ps
30
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing V
INPP
(min) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
– 2.0 V. Input edge rates
40 ps (20% − 80%).
12. Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of T
pw
− and T
pw
+ @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE
(mV)
800
700
600
Q AMP (mV)
V
CC
IN
500
V
T
400
300
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
f
in
, Clock Input Frequency (GHz)
IN
50
W
50
W
Figure 3. CLOCK Output Voltage Amplitude
(V
OUTPP
) vs. Input Frequency (f
in
) at Ambient
Temperature (Typ)
Figure 4. Input Structure
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