(*) XY - denotes the date code marking (2 digit) in production
TT - refers to die run/lot traceability for production
I - pin one indication
S - Product line designator
Note the Package Marking may change over the course of production time without notice
Order Number
10-Pin micro SMD
LM2612ATL
LM2612BTL
LM2612ATLX
LM2612BTLX
Package Type
NSC Package
Marking(*)
XYTT IS41A
Supplied As
250 Units, Tape and Reel
250 Units, Tape and Reel
3000 Units, Tape and Reel
3000 Units, Tape and Reel
TLP106WA
10-bump Wafer Level Chip Scale
(micro SMD)
XYTT IS41B
XYTT IS41A
XYTT IS41B
(*) XY - denotes the date code marking (2 digit) in production
TT - refers to die run/lot traceability for production
I - pin one indication
S - Product line designator
Note the Package Marking may change over the course of production time without notice
www.national.com
200418 Version 4 Revision 2
2
Print Date/Time: 2011/08/25 16:47:30
LM2612BL
Pin Description
Pin Number
A1
B1
C1
D1
Pin Name
FB
VID1
VID0
SYNC/MODE
Function
Feedback Analog Input. Connect to the output at the output filter capacitor (Figure 1)
Output Voltage Control Inputs. Set the output voltage using these digital inputs (see Table 1).
The output defaults to 1.5V if these pins are unconnected.
Synchronization Input. Use this digital input for frequency synchronization or modulation control.
Set:
SYNC/MODE = high for low-noise 600kHz PWM mode
SYNC/MODE = low for low-current PFM mode
SYNC/MODE = 500kHz - 1MHz external clock for synchronization to an external clock in PWM
mode. See
Synchronization and Operating Modes
in the
Device Information
section.
Enable Input. For shutdown, set low to SGND.(See
Shutdown Mode
in the
Device
Information
section.)
Power Ground
Switching Node connection to the internal PFET switch and NFET synchronous rectifier.
Power Supply Input to the internal PFET switch. Connect to the input filter capacitor (Figure
1).
Analog Supply Input. If board layout is not optimum, an optional 0.1µF ceramic capacitor is
suggested (Figure
1)
Analog and Control Ground
D2
D3
C3
B3
A3
A2
EN
PGND
SW
PVIN
VDD
SGND
(*) Note that the pin numbering scheme for the Micro SMD package was revised in April, 2002 to conform to JEDEC standard. Only the pin numbers were revised.
No changes to the physical location of the inputs/outputs were made. For reference purpose, the obselete numbering had FB as pin 1, VID1 as pin 2, VID0 as
pin 3, SYNC as pin 4, EN as pin 5, PGND as pin 6, SW as pin 7, PVIN as pin 8, VDD as pin 9 and SGND as pin 10.
3
200418 Version 4 Revision 2
Print Date/Time: 2011/08/25 16:47:30
www.national.com
LM2612BL
Absolute Maximum Ratings
(Note
1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
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