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DEVICE
SPECIFICATION
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
BiCMOS LVPECL OC-48 TRANSMITTER AND
CLOCK GENERATOR
SONET/SDH/ATM OC-12 16:1 TRANSMITTER RECEIVER
GENERAL DESCRIPTION
S3083
S3083
S3083
FEATURES
• Micro-power Bipolar supply
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLL for clock
generation
• Supports 2.488 Gbps (OC-48)
• Reference frequency of 155.52 MHz
• Interface to both LVPECL and LVTTL logic
• 16-bit LVPECL data path
• Compact 80 PQFP/TEP package
• Diagnostic loopback mode
• Line loopback
• Lock detect
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3V supply
The S3083 SONET/SDH MUX chip is a fully integrated
serialization SONET OC-48 (2.488 Gbps) interface de-
vice. The chip performs all necessary parallel-to-serial
functions in conformance with SONET/SDH transmis-
sion standards. The device is suitable for SONET-
based ATM applications. Figure 1 shows a typical
network application.
On-chip clock synthesis PLL components are con-
tained in the S3083 MUX chip allowing the use of a
slower external transmit clock reference. The chip
can be used with 155.52 MHz reference clock, in
support of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3083 is pack-
aged in a 80 PQFP/TEP, offering designers a small
package outline.
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
DWDM Systems
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
Network Interface
Processor
16
S3083
Tx
S3044
Rx
OTX
ORX
S3040
S3044
16
Rx
S3083
Tx
16
16
S3040
ORX
OTX
Network Interface
Processor
1
August 27, 1999 / Revision B
S3083
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
• Photonic
• Section
• Line
• Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signaling
rates.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
part of each STS-N signal is an optical carrier level-N
signal (OC-N). The S3083 chip supports the OC-48
data rate (2.488 Gbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-48
consists of 144 transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This
pattern of 144 overhead and 4176 SPE bytes is re-
peated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Figure 2. SONET Structure
Functions
Payload to
SPE mapping
Maintenance,
protection,
switching
Scrambling,
framing
Optical
transmission
Path layer
Line layer
Section layer
Path layer
Line layer
Section layer
Photonic layer
Photonic layer
End Equipment
Fiber Cable
End Equipment
Table 1. SONET Signal Hierarchy
Elec.
STS-1
STS-3
STS-12
STS-24
STS-48
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-N signal is made up of
N
byte-interleaved STS-1 signals. The optical counter-
CCITT
STM-1
STM-4
STM-8
STM-16
Optical Data Rate (Mbps)
OC-1
OC-3
OC-12
OC-24
OC-48
51.84
155.52
622.08
1244.16
2488.32
Figure 3. STS-48/OC-48 Frame Format
A1 A1
9 Rows
A1 A1
48 A1
Bytes
A2 A2
A2 A2
48 A2
Bytes
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
s
125
µsec
2
s
August 27, 1999 / Revision B
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3083 OVERVIEW
The S3083 transmitter implements SONET/SDH se-
rialization and transmission functions. The block dia-
gram in Figure 4 shows basic operation of the chip.
This chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip includes parallel-to-serial conversion
and system timing. The system timing circuitry con-
sists of a high-speed phase detector, clock dividers,
and clock distribution throughout the front end.
The sequence of operations is as follows:
S3083
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Internal clocking and control functions are transpar-
ent to the user. Details of the data timing can be
seen in Figure 7, 18, and 19.
Suggested Interface Devices
AMCC
AMCC
S3040
S3044
OC-48 Clock Recovery Device
OC-48 Receiver
Figure 4. S3083 Functional Block Diagram
DLEB
LLDP/N
LLCLKP/N
LLEB
16
16:1 PARALLEL
TO SERIAL
M
U
X
D
LSDP/N
TSDP/N
PIN[15:0]
PICLKP/N
LSCLKP/N
M 2
U
X
TSCLKP/N
PCLKP/N
PHINIT
TIMING
GEN
PHERR
TESTEN
CLOCK
DIVIDER and
PHASE DETECTOR
REFCLKP/N
RSTB
CAP1/2
2
LOCKDET
155MCK
August 27, 1999 / Revision B
3
S3083
S3083 ARCHITECTURE/FUNCTIONAL
DESIGN
MUX OPERATION
The S3083 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the byte serial 155.52 Mbyte/sec
data stream to bit serial format at 2.488 Gbps. Diag-
nostic loopback is provided (transmitter to receiver),
and Line Loopback is also provided (receiver to trans-
mitter).
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip phase-
locked loop circuit with a divider, VCO and loop filter.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Timing Generator
The Timing Generator function, seen in Figure 4, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
The PCLK output is a byte rate version of TSCLK.
For STS-48, the PCLK frequency is 155.52 MHz.
PCLK is intended for use as a byte speed clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3083 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to the TSCLK.
The Timing Generator also produces a feedback ref-
erence clock to the Phase Detector. A counter divides
the synthesized clock down to the same frequency
as the reference clock REFCLK.
Clock Divider and Phase Detector
The Clock Divider and Phase Detector, shown in the
block diagram in Figure 4, contains monolithic PLL
components that generate signals required to drive
the loop filter.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a fre-
quency accuracy of better than the value stated in
Table 7 in order for the VCOCLK frequency to have
the same accuracy required for operation in a
SONET system.
In order to meet the 0.01 UI SONET jitter specifica-
tions, the maximum reference clock jitter must be
guaranteed over the 12 kHz to 20 MHz bandwidth.
For details of reference clock jitter requirements, see
Table 2.
The on–chip phase detector, which compares the
phase relationship between the VCO input and the
REFCLK input, drives the loop filter.
Parallel-to-Serial Converter
The Parallel-to-Serial converter shown in Figure 4 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PIN[15:0]
bus on the rising edge of PICLK. The parallel-to-
serial register is a loadable shift register which takes
its parallel input from the FIFO output.
An internally generated divide by 16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.
Table 2. Reference Jitter Limits
Maximum Reference Clock
Jitter in 12 kHz to 20 MHz Band
1 ps rms
Operating
Mode
STS-48
4
August 27, 1999 / Revision B
RF/Wirelessly
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