700MH
Z
, L
OW
J
ITTER
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
Product Discontinuance Notice – Last Time Buy Expires on November 16, 2013
ICS8430-11
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS8430-11 is a general purpose, dual output Crystal-
to-3.3V Differential LVPECL High Frequency Synthesizer. The
ICS8430-11 has a selectable crystal oscillator interface or
LVCMOS TEST_CLK. The VCO operates at a frequency range
of 200MHz to 700MHz. With the output configured to divide
the VCO frequency by 2, output frequency steps as small as
2MHz can be achieved using a 16MHz crystal or reference
clock. Output frequencies up to 700MHz can be programmed
using the serial or parallel interfaces to the configuration logic.
The low jitter and frequency range of the ICS8430-11 make it
an ideal clock generator for most clock tree applications.
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface or
LVCMOS TEST_CLK
•
Output frequency up to 700MHz
•
Crystal input frequency range: 14MHz to 27MHz
•
VCO range: 200MHz to 700MHz
•
Parallel or serial interface for programming
counter and output dividers
•
RMS period jitter: 9.5ps (maximum)
•
Cycle-to-cycle jitter: 25ps (maximum)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL2
M4
M3
M2
M1
M0
V
CC
32 31 30 29 28 27 26 25
0
M5
M6
M7
M8
1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
XTAL1
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
TEST_CLK
16k
16k
16k
V
EE
XTAL1
OSC
XTAL2
÷
16
N0
N1
N2
V
EE
ICS8430-11
21
20
19
18
17
PLL
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
PHASE DETECTOR
VCO
÷
M
÷
2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
CONFIGURATION
INTERFACE
LOGIC
0
÷
N
1
MR
FOUT0
nFOUT0
FOUT1
nFOUT1
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
TEST
ICS8430EY-11 REVISION B DECEMBER 6, 2012
1
©2012
Integrated Device Technology, Inc.
ICS8430-11 Data Sheet
700MHz, Low Jitter Crystal-to-3.3V LVPECL Frequency Synthesizer
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-11 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 200MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-11 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remainsloaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hard-wired to set the M divider and N output divider to a
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
fxtal x 2M
fVCO =
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz refer-
ence are defined as 100
≤
M
≤
350. The frequency out is defined
as follows:
fout = fVCO = fxtal x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and N
outputdivider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
S_DATA
T1
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N2
M, N
nP_LOAD
t
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
ICS8430EY-11 REVISION B DECEMBER 6, 2012
2
©2012
Integrated Device Technology, Inc.
ICS8430-11 Data Sheet
700MHz, Low Jitter Crystal-to-3.3V LVPECL Frequency Synthesizer
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3,
28, 29, 30
31, 32
4
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5, M6, M7,
M0, M1, M2,
M3, M4
M8
N0, N1
N2
V
EE
TEST
V
CC
FOUT1,
nFOUT1
V
CCO
FOUT0,
nFOUT0
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
Pullup
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core power supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
18
S_CLOCK
Input
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
19
S_DATA
Input
Pulldown
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
20
S_LOAD
Input
Pulldown
LVCMOS / LVTTL interface levels.
Power
Analog supply pin.
21
V
CCA
Selects between crystal or test inputs as the PLL reference source.
22
XTAL_SEL
Input
Pullup
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Pulldown Test clock input. LVCMOS interface levels.
24, 25
XTAL1, XTAL2
Input
Crystal oscillator inputs.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input
Pulldown loaded into the M divider, and when data present at N2:N0 sets
the N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
27
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
K
K
ICS8430EY-11 REVISION B DECEMBER 6, 2012
3
©2012
Integrated Device Technology, Inc.
ICS8430-11 Data Sheet
700MHz, Low Jitter Crystal-to-3.3V LVPECL Frequency Synthesizer
Inputs
MR
H
L
L
L
L
L
L
nP_LOAD
X
L
H
H
H
H
M
X
Data
Data
X
X
X
X
N
X
Data
Data
X
X
X
X
S_LOAD
X
X
L
L
L
H
S_CLOCK
X
X
X
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
L
H
X
X
NOTE: L = LOW
H = HIGH
X = Don't care
= Rising edge transition
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
200
202
204
206
•
•
M Divide
100
101
102
103
•
•
256
M8
0
0
0
0
•
•
128
M7
0
0
0
0
•
•
64
M6
1
1
1
1
•
•
32
M5
1
1
1
1
•
•
16
M4
0
0
0
0
•
•
8
M3
0
0
0
0
•
•
4
M2
1
1
1
1
•
•
2
M1
0
0
1
1
•
•
1
M0
0
1
0
1
•
•
0
1
0
696
348
1
0
1
0
1
1
698
349
1
0
1
0
1
1
700
350
1
0
1
0
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK
16MHz.
1
0
1
0
1
1
input frequency of
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider Value
2
4
8
16
1
2
4
8
FOUT0, nFOUT0 Output Frequency
(MHz)
Minimum
Maximum
100
350
50
25
12.5
200
100
50
25
175
87.5
43.75
700
350
175
87.5
ICS8430EY-11 REVISION B DECEMBER 6, 2012
4
©2012
Integrated Device Technology, Inc.
ICS8430-11 Data Sheet
700MHz, Low Jitter Crystal-to-3.3V LVPECL Frequency Synthesizer
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
140
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
Input
High Voltage
Parameter
TEST_CLK; NOTE 1
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
TEST_CLK; NOTE 1
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
M0:M8, N0:N2, XTAL_SEL
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
M8, N2, XTAL_SEL, VCO_SEL
TEST_CLK
Input
Low Current
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
TEST_CLK, M8, N2,
XTAL_SEL, VCO_SEL
Test Conditions
Minimum
2.35
2
-0.3
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
2.6
0.5
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.95
0.8
150
5
200
Units
V
V
V
V
µA
µA
µA
µA
µA
V
V
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Output
TEST; NOTE 2
High Voltage
Output
V
OL
TEST; NOTE 2
Low Voltage
NOTE 1: Characterized with 1ns input edge rate.
NOTE 2: Outputs terminated with 50 to V
CCO
/2.
V
OH
ICS8430EY-11 REVISION B DECEMBER 6, 2012
5
©2012
Integrated Device Technology, Inc.
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