IDT49C403GB datasheet, PDF - EEWORLD Datasheet

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IDT49C403GB: DescriptionBit-Slice Processor, 32-Bit, CMOS, CPGA108, CAVITY-UP, PGA-108; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，32 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT49C403GB Overview

Bit-Slice Processor, 32-Bit, CMOS, CPGA108, CAVITY-UP, PGA-108

IDT49C403GB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	PGA
package instruction	CAVITY-UP, PGA-108
Contacts	108
Reach Compliance Code	not_compliant
ECCN code	3A001.A.2.C
External data bus width	32
JESD-30 code	S-CPGA-P108
JESD-609 code	e0
length	30.48 mm
Number of terminals	108
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA108(UNSPEC)
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.207 mm
Maximum slew rate	275 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	30.48 mm
uPs/uCs/peripheral integrated circuit type	BIT-SLICE MICROPROCESSOR

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IDT49C403GB Related Products

	IDT49C403GB	IDT49C403G	IDT49C403AG	IDT49C403AGB
Description	Bit-Slice Processor, 32-Bit, CMOS, CPGA108, CAVITY-UP, PGA-108	Bit-Slice Processor, 32-Bit, CMOS, CPGA108, CAVITY-UP, PGA-108	Bit-Slice Processor, 32-Bit, CMOS, CPGA108, CAVITY-UP, PGA-108	Bit-Slice Processor, 32-Bit, CMOS, CPGA108, CAVITY-UP, PGA-108
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	PGA	PGA	PGA	PGA
package instruction	CAVITY-UP, PGA-108	CAVITY-UP, PGA-108	CAVITY-UP, PGA-108	CAVITY-UP, PGA-108
Contacts	108	108	108	108
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant
External data bus width	32	32	32	32
JESD-30 code	S-CPGA-P108	S-CPGA-P108	S-CPGA-P108	S-CPGA-P108
JESD-609 code	e0	e0	e0	e0
length	30.48 mm	30.48 mm	30.48 mm	30.48 mm
Number of terminals	108	108	108	108
Maximum operating temperature	125 °C	70 °C	70 °C	125 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA	PGA	PGA
Encapsulate equivalent code	PGA108(UNSPEC)	PGA108(UNSPEC)	PGA108(UNSPEC)	PGA108(UNSPEC)
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.207 mm	5.207 mm	5.207 mm	5.207 mm
Maximum slew rate	275 mA	250 mA	250 mA	275 mA
Maximum supply voltage	5.5 V	5.25 V	5.25 V	5.5 V
Minimum supply voltage	4.5 V	4.75 V	4.75 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	COMMERCIAL	COMMERCIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	30.48 mm	30.48 mm	30.48 mm	30.48 mm
uPs/uCs/peripheral integrated circuit type	BIT-SLICE MICROPROCESSOR	BIT-SLICE MICROPROCESSOR	BIT-SLICE MICROPROCESSOR	BIT-SLICE MICROPROCESSOR

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