NIS5132 Series
+12 Volt Electronic Fuse
The NIS5132 is a cost effective, resettable fuse which can greatly
enhance the reliability of a hard drive or other circuit from both
catastrophic and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits. It also includes an overvoltage
clamp circuit that limits the output voltage during transients but does
not shut the unit down, thereby allowing the load circuit to continue
operation. Two thermal options are available, latching and auto−retry.
Features
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3.6 AMP, 12 VOLT
ELECTRONIC FUSE
•
•
•
•
•
•
•
•
•
Integrated Power Device
Power Device Thermally Protected
No External Current Shunt Required
9 V to 18 V Input Range
44 mW Typical
Internal Charge Pump
Internal Undervoltage Lockout Circuit
Internal Overvoltage Clamp (MN1 and MN2 versions)
ESD Ratings: Human Body Model (HBM); 2000 V
Machine Model (MM); 200 V
•
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
DFN10
CASE 485C
MARKING DIAGRAM
1
32
AYWG
G
Pin
1
2
3
4
5
6−10
11 (flag)
Function
GND
dv/dt
Enable/Fault
ILIMIT
NC
SOURCE
VCC
•
Hard Drives
•
Mother Board Power Management
32
32B
32H
A
Y
W
G
= Latching Version with V
Clamp
= Latching Version without V
Clamp
= Auto−Retry Version with V
Clamp
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
July, 2014
−
Rev. 10
1
Publication Order Number:
NIS5132/D
NIS5132 Series
VCC
ENABLE/
FAULT
Enable
Charge
Pump
SOURCE
Thermal
Shutdown
Current
Limit
I
LIMIT
UVLO
Voltage
Clamp*
dv/dt
Control
dv/dt
(*MN1 and MN2 versions)
Figure 1. Block Diagram
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
1
2
Function
Ground
dv/dt
GND
Description
Negative input voltage to the device. This is used as the internal reference for the IC.
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal
capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to
this pin to increase the ramp time. If an additional time delay is not required, this pin should be left
open.
The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the
output of the device by pulling it to ground using an open drain or open collector device. If a
thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring
circuit that the device is in thermal shutdown. It can also be connected to another device in this
family to cause a simultaneous shutdown during thermal events.
A resistor between this pin and the source pin sets the overload and short circuit current limit
levels.
This pin is the source of the internal power FET and the output terminal of the fuse.
Positive input voltage to the device.
3
Enable/Fault
4
6−10
11 (belly pad)
I
Limit
Source
V
CC
MAXIMUM RATINGS
Rating
Input Voltage, operating, steady−state (V
CC
to GND, Note 1)
Transient (100 ms)
Thermal Resistance, Junction−to−Air
0.1 in
2
copper (Note 2)
0.5 in
2
copper (Note 2)
Thermal Resistance, Junction−to−Lead (Pin 1)
Thermal Resistance, Junction−to−Case
Total Power Dissipation @ T
A
= 25°C
Derate above 25°C
Operating Temperature Range (Note 3)
Nonoperating Temperature Range
Lead Temperature, Soldering (10 Sec)
Symbol
V
IN
q
JA
Value
−0.6
to 18
−0.6
to 25
227
95
27
20
1.3
10.4
−40
to 150
−55
to 155
260
Unit
V
°C/W
q
JL
q
JC
P
max
T
J
T
J
T
L
°C/W
°C/W
W
mW/°C
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package.
2. 1 oz. copper, double−sided FR4.
3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the
maximum ratings for extended periods of time.
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2
NIS5132 Series
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: V
CC
= 12 V, C
L
= 100
mF,
dv/dt pin open, R
LIMIT
= 10
W,
T
j
= 25°C
unless otherwise noted.)
Characteristics
POWER FET
Delay Time (enabling of chip to I
D
= 100 mA with 1 A resistive load)
Kelvin ON Resistance (Note 4)
T
J
= 140°C (Note 5)
Off State Output Voltage
(V
CC
= 18 V
dc
, V
GS
= 0 V
dc
, R
L
=
R)
Output Capacitance (V
DS
= 12 V
dc
, V
GS
= 0 V
dc
, f = 1 MHz)
Continuous Current (T
A
= 25°C, 0.5 in
2
pad) (Note 5)
(T
A
= 80°C, minimum copper)
THERMAL LATCH
Shutdown Temperature (Note 5)
Thermal Hysteresis (Decrease in die temperature for turn on, does not apply
to latching parts)
UNDER/OVERVOLTAGE PROTECTION
Output Clamping Voltage (Overvoltage Protection) (V
CC
= 18 V) (Note 6)
Undervoltage Lockout (Turn on, voltage going high)
UVLO Hysteresis
CURRENT LIMIT
Kelvin Short Circuit Current Limit (R
Limit
= 15.4
W,
Note 7)
Kelvin Overload Current Limit (R
Limit
= 15.4
W,
Note 7)
dv/dt CIRCUIT
Output Voltage Ramp Time (Enable to V
OUT
= 11.7 V)
Maximum Capacitor Voltage
ENABLE/FAULT
Logic Level Low (Output Disabled)
Logic Level Mid (Thermal Fault, Output Disabled)
Logic Level High (Output Enabled)
High State Maximum Voltage
Logic Low Sink Current (V
enable
= 0 V)
Logic High Leakage Current for External Switch (V
enable
= 3.3 V)
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
TOTAL DEVICE
Bias Current (Operational)
Bias Current (Shutdown)
Minimum Operating Voltage (Notes 5 and 8)
I
Bias
I
Bias
V
min
1. 8
1.0
7.6
2.5
mA
mA
V
V
in−low
V
in−mid
V
in−high
V
in−max
I
in−low
I
in−leak
Fan
0.35
0.82
1.96
3.40
0.58
1.4
2.64
4.30
−17
0.81
1.95
3.30
5.2
−25
1.0
3.0
V
V
V
V
mA
mA
Units
t
slew
V
max
0.5
0.9
1.8
V
CC
ms
V
I
Lim−SS
I
Lim−OL
2.75
3.44
4.6
4.25
A
A
V
Clamp
V
UVLO
V
Hyst
14
7.7
−
15
8.5
0.80
16.2
9.3
−
V
V
V
T
SD
T
Hyst
150
175
45
200
°C
°C
I
D
I
D
T
dly
R
DSon
V
off
35
220
44
62
190
250
3.6
1.7
55
300
ms
mW
mV
pF
A
Symbol
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse test: Pulse width 300
ms,
duty cycle 2%.
5. Verified by design.
6. V
Clamp
only in MN1 & MN2 versions.
7. Refer to explanation of short circuit and overload conditions in application note AND8140.
8. Device will shut down prior to reaching this level based on actual UVLO trip point.
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3
NIS5132 Series
60
50
25_C
POWER (W)
40
30
20
10
0
80_C
50_C
0.1
1
10
100
TIME (ms)
1000
10000 100000
Figure 2. Power Dissipation vs. Thermal Trip Time
+12 V
11 V
CC
SOURCE
NIS5132
I
LIMIT
ENABLE
10
9
8
7
6
4
R
S
3
GND
ENABLE
1
dv/dt
2
LOAD
GND
Figure 3. Application Circuit with Direct Current Sensing
+12 V
11 V
CC
SOURCE
NIS5132
I
LIMIT
ENABLE
10
9
8
7
6
4
R
S
3
GND
ENABLE
1
dv/dt
2
LOAD
GND
Figure 4. Application Circuit with Kelvin Current Sensing
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4
NIS5132 Series
V
CC
SOURCE
V
CC
SOURCE
R
S
NIS5135
I
LIMIT
ENABLE
ENABLE
NIS5132
I
LIMIT
LOAD
dv/dt
GND
ENABLE
GND
dv/dt
LOAD
Figure 5. Common Thermal Shutdown
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