ADVANCE D COM P ON E NTS PACKAG I NG
128 Megabit Synchronous DRAM
DPSD4MX32RY5
PIN-OUT DIAGRAM
DESCRIPTION:
The LP-Stack™ series is a family of interchangeable memory
modules. The 128 Megabit SDRAM is a member of this family
which utilizes the new and innovative space saving TSOP
stacking technology. The modules are constructed with
4 Meg x 16 SDRAMs.
This 128 Megabit LP-Stack™ module, DPSD4MX32RY5, has
been designed to allow 32 Output Data lines utilizing two 4
Meg x16 SDRAM TSOP monolithics. Utilizing this LP-Stack™
family allows the memory board designer to upgrade the
memory in their products without redesigning the memory
board, thus saving time and money.
FEATURES:
• Configuration Available:
4 Meg x 32 bit
• Clock Frequency:
66, 83, 100, 125, 133 MHz (max.)
• PC100 and PC133 Compatible
• 3.3V Supply
• LVTTL Compatible I/O
• Four Bank Operation
• Programmable Burst Type, Burst Length, and CAS Latency
• 4096 Cycles / 64 ms
• Auto and Self Refresh
• Package: TSOP Leadless Stack
DQ27
DQ26
DQ25
DQ24
VSS
UDQM1
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM0
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
LDQM1
VDD
DQ23
DQ22
DQ21
DQ20
VSS
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VDD
DQ28
DQ29
DQ30
DQ31
VSS
N.C.
(TOP VIEW)
VSS
DQ15
VDDQ
DQ14
DQ13
VSSQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
N.C.
UDQM0
CK
CKE
N.C.
A11
A9
A8
A7
A6
A5
A4
VSS
N.C.
VDD
DQ16
DQ17
DQ18
DQ19
R
E
L
I
M
I
N
A
R
Y
P
PIN NAMES
A0-A11
BA0,BA1
DQ0-DQ31
CS
CAS
RAS
WE
Row Address:
A0-A11
Column Address: A0-A7
Bank Select Address
Data In/Data Out
Chip Select
Column Address Strobe
Row Address Enable
Data Write Enable
UDQM1
LDQM1
UDQM0
LDQM0
CS
WE
RAS
CAS
CKE
CK
DM
A0-A11
BA0-BA1
FUNCTIONAL BLOCK DIAGRAM
UDQM0,UDQM1 Upper Data Input/Output Masks
LDQM0,LDQM1 Lower Data Input/Output Masks
CKE
CLK
V
DD
/Vss
Vcc
Q
/Vss
Q
Clock Enable
System Clock
Power Supply/Ground
Data Output Power/Ground
4Mx16 SDRAM
4Mx16 SDRAM
DQ16-DQ31
DQ0-DQ15
30A225-02
REV. E 8/01
This document contains information on a product presently under development at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
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128 Megabit Synchronous DRAM
DPSD4MX32RY5
ORDERING INFORMATION
DP
PREFIX
SD
4M
X
32
R
DESIG
Y5
PACKAGE
- DP - XX
SUPPLIER
MEMORY
XX
SPEED
X
CL
X
[1]
TYPE MEMORY
DEPTH
DESIG MEMORY
WIDTH
GRADE
Blank Commercial Temperature
2
15
12
10
08
75
P1
CAS LATENCY 2
15ns (66MHz)
12ns (83MHz)
10ns (100MHz)
8ns (125MHz)
7.5ns (133MHz)
PC100
[1]
[1]
MANUFACTURER CODE
SUPPLIER CODE
STACKABLE TSOP
64 MEGABIT LVTTL BASED
MEMORY MODULE WITHOUT SUPPORT LOGIC
SYNCHRONOUS DRAM
Y
NOTE:
N
A
R
[1] Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
I
M
.502±.008
[12.75±.20]
.062
[1.57] (X4)
.078
[2.01] (X4)
E
L
I
.0315
[0.80]
.975±.010
[24.77±.25]
.020
[0.51]
P
R
.042
[0.79]
.0275
[0.79]
.155 MAX.
[3.94] MAX.
.015
[0.38]
Dimensions - Inches [mm]
30A225-02
REV. E 8/01
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
©2001 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, CS Stack™ are trademarks of DPAC Technologies Corp.
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