PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874S02I
1:1 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
EATURES
•
One differential LVDS output pair designed to meet
or exceed the requirements of ANSI TIA/EIA-644,
One differential feedback output pair
•
Differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL
•
Output frequency range: 62.5MHz to 1GHz
•
Input frequency range: 62.5MHz to 1GHz
•
VCO range: 500MHz to 1GHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
Cycle-to-cycle jitter: 26ps (typical)
•
Output skew: 4ps (typical)
•
Static phase offset: 98ps (typical)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS874S02I is a highly versatile 1:1 LVDS
Clock Generator and a member of the
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS874S02I has a fully
integrated PLL and can be configured as zero
delay buffer, multiplier or divider, and has an output frequency
range of 62.5MHz to 1GHz. The Reference Divider, Feed-
back Divider and Output Divider are each programmable,
thereby allowing for the following output-to-input frequency
ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback
allows the device to achieve “zero delay” between the input
clock and the output clock. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
IC
S
B
LOCK
D
IAGRAM
PLL_SEL
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
P
IN
A
SSIGNMENT
0
1
Q
nQ
QFB
nQFB
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
V
DDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
CLK
nCLK
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
nFB_IN
ICS874S02I
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
874S02AMI
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 27, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874S02I
1:1 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Type
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7, 11
8, 9
10, 14
12, 13
15
16
17
18
19
20
Name
CLK
nCLK
MR
nFB_IN
FB_IN
SEL 2
V
DDO
GND
nQ, Q
SEL3
V
DDA
PLL_SEL
V
DD
SEL0
SEL1
Input
Input
Input
Input
Input
Input
Power
Power
Output
Input
Power
Input
Power
Input
Input
Pullup
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
Pullup
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Output supply pins.
Differential feedback outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When HIGH, selects PLL. When LOW, selects the reference clock.
LVCMOS / LVTTL interface levels.
Core supply pin.
nQFB, QFB Output
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
874S02AMI
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 27, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874S02I
1:1 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Outputs
PLL_SEL = 1
PLL Enable Mode
Q , nQ
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)*
500 - 1000
250 - 500
125 - 250
62.5 - 125
500 - 1000
250 - 500
125 - 250
500 - 1000
250 - 500
500 - 1000
250 - 500
125 - 250
62.5 - 125
125 - 250
62.5 - 125
62.5 - 125
*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
874S02AMI
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q , nQ
÷4
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
REV. A APRIL 27, 2006
www.icst.com/products/hiperclocks.html
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874S02I
1:1 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
46.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
- 0.18
3.135
Typical
3.3
3.3
3.3
84
18
30
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
V
CMR
Input High Current
Input Low Current
CLK, FB_IN
nCLK, nFB_IN
CLK, FB_IN
nCLK0, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
874S02AMI
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 27, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874S02I
1:1 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Test Conditions
Minimum
Typical
440
0
1.27
25
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
IN
Parameter
Input Frequency
CLK,
nCLK
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
62.5
Typical
Maximum
1000
1000
Units
MH z
MH z
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(Ø)
t
sk(o)
t
jit(cc)
odc
t
L
Parameter
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter ; NOTE 4, 5
Output Duty Cycle
PLL Lock Time
PLL_SEL = 3.3V
Test Conditions
Minimum
62.5
1.85
98
4
26
50
1
Typical
Maximum
1000
Units
MHz
ns
ps
ps
ps
%
ms
ps
Output Rise/Fall Time; NOTE 6
180
t
R
/ t
F
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Characterized at VCO frequency of 800MHz.
NOTE 6: Measured from the 20% to 80% points.
874S02AMI
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 27, 2006
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