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28C17A-15/J

Description
2K X 8 EEPROM 5V, 150 ns, CDIP28, 0.600 INCH, CERDIP-28
Categorystorage    storage   
File Size67KB,8 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

28C17A-15/J Overview

2K X 8 EEPROM 5V, 150 ns, CDIP28, 0.600 INCH, CERDIP-28

28C17A-15/J Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeDIP
package instructionDIP, DIP28,.6
Contacts28
Reach Compliance Code_compli
ECCN codeEAR99
Maximum access time150 ns
Other featuresAUTOMATIC WRITE; BULK ERASE; 10K ERASE/WRITE CYCLES MIN.; 1MS BYTE WRITE; DATA RETENTION > 10 YEARS
command user interfaceNO
Data pollingYES
Data retention time - minimum10
Durability10000 Write/Erase Cycles
JESD-30 codeR-GDIP-T28
JESD-609 codee0
length36.83 mm
memory density16384 bi
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals28
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2KX8
Output characteristics3-STATE
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
ready/busyYES
Maximum seat height5.461 mm
Maximum standby current0.0001 A
Maximum slew rate0.032 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
switch bitNO
width15.24 mm
Maximum write cycle time (tWC)1 ms
Base Number Matches1
28C17A
16K (2K x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100
µ
A Standby
• Fast Byte Write Time—200
µ
s or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 10
4
Erase/Write Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling; Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
- 28 Pin Dual-In-Line Package
- 32-Pin PLCC Package
- 28-Pin Thin Small Outline Package (TSOP)
8x20mm
- 28-Pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
PACKAGE TYPES
RDY/BSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
NC
A8
A6
5
A9
A5
6
NC
A4
7
A3
8
OE
A10 A2
9
A1
10
CE
A0
11
I/O7
NC
12
I/O6
I/O0
13
I/O5
I/O4
I/O3
2
RDY/BSY
1
NU
32
Vcc
31
WE
18
19
4
A7
3
NC
30
NC
29
A8
28
A9
27
NC
26
NC
25
OE
24
A10
23
CE
22
I/O7
21
I/O6
20
14
15
16
• Pin 1 indicator on PLCC on top of package
OE
NC
A9
A8
NC
WE
Vcc
RDY/BSY
NC
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
23
24
25
26
27
28
1
2
3
4
5
6
7
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
17
DIP/SOIC
PLCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A10
CE
I/07
I/06
I/05
I/04
I/03
Vss
I/02
I/01
I/00
A0
A1
A2
TSOP
OE
NC
A9
A8
NC
WE
V
CC
RDY/BSY
NC
A7
A6
A5
A4
A3
VSOP
DESCRIPTION
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
volatile electrically Erasable PROM. The 28C17A is
accessed like a static RAM for the read or write cycles without
the need of external components. During a “byte write”, the
address and data are latched internally, freeing the micropro-
cessor address and data bus for other operations. Following
the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an
internal control timer. To determine when the write cycle is
complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications.
BLOCK DIAGRAM
I/O0
I/O7
V
SS
V
CC
CE
OE
WE
Rdy/
Busy
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Data
Poll
Input/Output
Buffers
Program Voltage
Generation
A0
L
a
t
c
h
e
s
A10
Y
Decoder
Y Gating
X
Decoder
16K bit
Cell Matrix
©
1996 Microchip Technology Inc.
DS11127G-page 1
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