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SCES224M − APRIL 1999 − REVISED JUNE 2005
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
D
Available in the Texas Instruments
D
D
D
D
D
NanoStar and NanoFree Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 3.7 ns at 3.3 V
Low Power Consumption, 10-µA Max I
CC
±24-mA
Output Drive at 3.3 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
D
I
off
Supports Partial-Power-Down Mode
D
D
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
OE
A
GND
1
5
V
CC
OE
A
1
2
3
5
V
CC
OE
A
GND
1
2
3
5
V
CC
Y
GND
A
OE
3 4
2
1 5
Y
V
CC
2
4
GND
4
4
Y
3
Y
See mechanical drawings for dimensions.
description/ordering information
This single bus buffer gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is low.
ORDERING INFORMATION
TA
PACKAGE†
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Reel of 3000
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
SOT (SOT-553) − DRL
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
Reel of 3000
SN74LVC1G126YEPR
SN74LVC1G126YZPR
SN74LVC1G126DBVR
SN74LVC1G126DBVT
SN74LVC1G126DCKR
SN74LVC1G126DCKT
SN74LVC1G126DRLR
CN_
CN_
C26_
ORDERABLE
PART NUMBER
SN74LVC1G126YEAR
SN74LVC1G126YZAR
_ _ _CN_
TOP-SIDE
MARKING‡
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SCES224M − APRIL 1999 − REVISED JUNE 2005
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OE
H
H
L
A
H
L
X
OUTPUT
Y
H
L
Z
logic diagram (positive logic)
1
OE
A
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±100
mA
Package thermal impedance,
θ
JA
(see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SCES224M − APRIL 1999 − REVISED JUNE 2005
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
recommended operating conditions (see Note 4)
MIN
Operating
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
IOL
Low-level output current
VCC = 3 V
VCC = 4.5 V
VCC = 1.8 V
±
0.15 V, 2.5 V
±
0.2 V
∆t/∆v
Input transition rise or fall rate
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
1.65
1.5
0.65
×
VCC
1.7
2
0.7
×
VCC
0.35
×
VCC
0.7
0.8
0.3
×
VCC
5.5
VCC
−4
−8
−16
−24
−32
4
8
16
24
32
20
10
5
ns/V
mA
mA
V
V
V
V
MAX
5.5
V
UNIT
VIH
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCES224M − APRIL 1999 − REVISED JUNE 2005
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = −100
mA
IOH = −4 mA
VOH
IOH = −8 mA
IOH = −16 mA
IOH = −24 mA
IOH = −32 mA
IOL = 100
mA
IOL = 4 mA
VOL
IOL = 8 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
II
Ioff
IOZ
ICC
∆I
CC
Ci
A or OE inputs
VI = 5.5 V or GND
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = 5.5 V or GND,
One input at VCC − 0.6 V,
IO = 0
Other inputs at VCC or GND
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
0 to 5.5 V
0
3.6 V
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
4
MIN
VCC−0.1
1.2
1.9
2.4
2.3
3.8
0.1
0.45
0.3
0.4
0.55
0.55
±5
±10
10
10
500
mA
mA
mA
mA
mA
pF
V
V
TYP†
MAX
UNIT
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, C
L
= 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
VCC = 1.8 V
±
0.15 V
MIN
1.7
MAX
6.9
VCC = 2.5 V
±
0.2 V
MIN
0.6
MAX
4.6
VCC = 3.3 V
±
0.3 V
MIN
0.6
MAX
3.7
VCC = 5 V
±
0.5 V
MIN
0.5
MAX
3.4
ns
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 30 pF or
50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
A
OE
OE
TO
(OUTPUT)
Y
Y
Y
VCC = 1.8 V
±
0.15 V
MIN
2.6
2.8
1.6
MAX
8
9.4
9.8
VCC = 2.5 V
±
0.2 V
MIN
1.1
1.3
1
MAX
5.5
6.6
5.5
VCC = 3.3 V
±
0.3 V
MIN
1
1.2
1
MAX
4.5
5.3
5.5
VCC = 5 V
±
0.5 V
MIN
1
1
1
MAX
4
5
4.2
ns
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation
capacitance
Outputs enabled
Outputs disabled
f = 10 MHz
TEST
CONDITIONS
VCC = 1.8 V
TYP
19
2
VCC = 2.5 V
TYP
19
2
VCC = 3.3 V
TYP
19
3
VCC = 5 V
TYP
21
4
pF
UNIT
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PCB Design
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