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PA28F400BV-B120

Description
512KX8 FLASH 5V PROM, 180ns, PDSO44, 0.525 X 1.110 INCH, PLASTIC, SOP-44
Categorystorage    storage   
File Size649KB,57 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

PA28F400BV-B120 Overview

512KX8 FLASH 5V PROM, 180ns, PDSO44, 0.525 X 1.110 INCH, PLASTIC, SOP-44

PA28F400BV-B120 Parametric

Parameter NameAttribute value
Parts packaging codeSOIC
package instructionSOP,
Contacts44
Reach Compliance Codeunknow
Maximum access time180 ns
Other featuresCAN BE OPERATED IN 4.5V TO 5.5V; CAN BE CONFG AS 256K X 16; BOTTOM BOOT BLOCK
JESD-30 codeR-PDSO-G44
length28.2 mm
memory density4194304 bi
Memory IC TypeFLASH
memory width8
Number of functions1
Number of terminals44
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height2.95 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width13.3 mm
Base Number Matches1
E
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PRELIMINARY
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B
Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Increased Programming Throughput
at 12V V
PP
Very High-Performance Read
5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at
2.7V–3.6V
x8/x16-Selectable Input/Output Bus
28F400 for High Performance 16- or
32-bit CPUs
x8-Only Input/Output Architecture
28F004B for Space-Constrained
8-bit Applications
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
Absolute Hardware-Protection for Boot
Block
Software EEPROM Emulation with
Parameter Blocks
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Extended Temperature Operation
–40°C to +85°C
Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical I
CC
Active Current in
Static Operation
Reset/Deep Power-Down Input
0.2 µA I
CC
Typical
Provides Reset for Boot Operations
Hardware Data Protection Feature
Write Lockout during Power
Transitions
Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
56-Lead TSOP
Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
ETOX™ IV Flash Technology
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July 1997
Order Number: 290530-005

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