74LVC1G3208DCKRE4 datasheet, PDF

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74LVC1G3208DCKRE4: DescriptionLogic Gates Sgl 3Input Pos OR- AND Gate; Categorylogic logic; File Size592KB，16 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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74LVC1G3208DCKRE4 Overview

Logic Gates Sgl 3Input Pos OR- AND Gate

74LVC1G3208DCKRE4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	TSSOP, TSSOP6,.08
Contacts	6
Reach Compliance Code	unknown
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G6
JESD-609 code	e4
length	2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	OR-AND GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	1
Number of entries	3
Number of terminals	6
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP6,.08
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	5.9 ns
propagation delay (tpd)	17.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	1.25 mm
Base Number Matches	1

74LVC1G3208DCKRE4 Related Products

	74LVC1G3208DCKRE4	74LVC1G3208DBVTE4	74LVC1G3208DCKRG4	74LVC1G3208DCKTG4	74LVC1G3208DCKTE4
Description	Logic Gates Sgl 3Input Pos OR- AND Gate	Logic Gates Sgl 3Input Pos OR- AND Gate	Logic Gates Sgl 3Input Pos OR- AND Gate	Logic Gates Sgl 3Input Pos OR- AND Gate	Logic Gates Sgl 3Input Pos OR- AND Gate
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Parts packaging code	SOIC	SOT-23	SOIC	SOIC	SOIC
package instruction	TSSOP, TSSOP6,.08	LSSOP, TSOP6,.11,37	TSSOP, TSSOP6,.08	TSSOP, TSSOP6,.08	TSSOP, TSSOP6,.08
Contacts	6	6	6	6	6
Reach Compliance Code	unknown	unknow	unknow	unknow	unknow
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G6	R-PDSO-G6	R-PDSO-G6	R-PDSO-G6	R-PDSO-G6
JESD-609 code	e4	e4	e4	e4	e4
length	2 mm	2.9 mm	2 mm	2 mm	2 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	OR-AND GATE	OR-AND GATE	OR-AND GATE	OR-AND GATE	OR-AND GATE
MaximumI(ol)	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	1	1	1	1
Number of functions	1	1	1	1	1
Number of entries	3	3	3	3	3
Number of terminals	6	6	6	6	6
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	LSSOP	TSSOP	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP6,.08	TSOP6,.11,37	TSSOP6,.08	TSSOP6,.08	TSSOP6,.08
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
propagation delay (tpd)	17.5 ns	17.5 ns	17.5 ns	17.5 ns	17.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO
Maximum seat height	1.1 mm	1.45 mm	1.1 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.95 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	1.25 mm	1.6 mm	1.25 mm	1.25 mm	1.25 mm
Base Number Matches	1	1	1	1	1
Prop。Delay @ Nom-Su	-	5.9 ns	5.9 ns	5.9 ns	5.9 ns

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