CAT33C804BPC datasheet, PDF - EEWORLD Datasheet

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CAT33C804BPC: DescriptionEEPROM, 256X16, Serial, CMOS, PDIP8; Categorystorage storage; File Size89KB，14 Pages; ManufacturerCatalyst; Websitehttp://www.catalyst-semiconductor.com/

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CAT33C804BPC Overview

EEPROM, 256X16, Serial, CMOS, PDIP8

CAT33C804BPC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Catalyst
package instruction	DIP, DIP8,.3
Reach Compliance Code	unknown
Spare memory width	8
Data retention time - minimum	100
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
memory density	4096 bit
Memory IC Type	EEPROM
memory width	16
Number of terminals	8
word count	256 words
character code	256
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256X16
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP8,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	SERIAL
power supply	3 V
Certification status	Not Qualified
Maximum standby current	0.00025 A
Maximum slew rate	0.003 mA
Nominal supply voltage (Vsup)	3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
write protect	SOFTWARE

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Preliminary

CAT33C804A

4K-Bit Secure Access Serial E

PROM

FEATURES

Single 3V Supply

Password READ/WRITE Protection: 1 to 8 Bytes

Memory Pointer WRITE Protection

Sequential READ Operation

256 x 16 or 512 x 8 Selectable Serial Memory

UART Compatible Asynchronous Protocol

Commercial, Industrial and Automotive

100,000 Program/Erase Cycles

I/O Speed: 9600 Baud

–Clock Frequency: 4.9152 MHz Xtal

Low Power Consumption:

–Active: 3 mA

–Standby: 250

100 Year Data Retention

Temperature Ranges

DESCRIPTION

The CAT33C804A is a 4K-bit Serial E

PROM that safe-

guards stored data from unauthorized access by use of

a user selectable (1 to 8 byte) access code and a

movable memory pointer. Two operating modes provide

unprotected and password-protected operation allow-

ing the user to configure the device as anything from a

ROM to a fully protected no-access memory. The

CAT33C804A uses a UART compatible asynchronous

protocol and has a Sequential Read feature where data

can be sequentially clocked out of the memory array.

The device is available in 8-pin DIP or 16-pin SOIC

packages.

PIN CONFIGURATION

DIP Package (P)

CLK

VCC

ERR

GND

BLOCK DIAGRAM

SOIC Package (J)

VCC

ERR

GND

5074 FHD F01

CLK

VCC

GND

64-BIT ACCESS CODE

CONTROL BLOCK

SERIAL

COMMUNI-

CATION

BLOCK

PIN FUNCTIONS

Pin Name

(1)

CLK

(1)

ERR

GND

Function

Chip Select

Serial Data Output

Clock Input

Serial Data Input

Parity Enable

Error Indication Pin

+3V Power Supply

Ground

CLK

4K-BIT EEPROM

ARRAY

R/W

BUFFER

ADDRESS

DECODER

INSTRUCTION

ERR

INSTRUCTION

DECODER

ADDRESS

STATUS

MEMORY

POINTER

Note:

(1) DI, DO may be tied together to form a common I/O.

Characteristics subject to change without notice

33C804 F02

Doc. No. 25044-00 2/98

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