Analog Input .............................................................. 0V to (+V
S
+ 300mV)
Logic Input ................................................................ 0V to (+V
S
+ 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB) .............................. +1.1V Min
NOTE: (1) Stresses above these ratings may permanently damage the device.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
(1)
PACKAGE
DESIGNATOR
DW
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
ADS800U
ORDERING
NUMBER
ADS800U
TRANSPORT
MEDIA, QUANTITY
Rails, 28
PRODUCT
ADS800U
PACKAGE-LEAD
SO-28
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At T
A
= +25°C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS800U
PARAMETER
Resolution
Specified Temperature Range
Operating Temperature Range
ANALOG INPUT
Differential Full-Scale Input Range
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small-Signal
Full-Power
Input Impedance
DIGITAL INPUT
Logic Family
Convert Command
ACCURACY
(2)
Gain Error
Gain Drift
Power-Supply Rejection of Gain
Input Offset Error
Power-Supply Rejection of Offset
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
f = 12MHz
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
t
H
= 13ns
(3)
CONDITIONS
T
AMBIENT
T
AMBIENT
Both Inputs,
180° Out-of-Phase
TEMP
MIN
0
–40
+1.25
+2.25
–20dBFS
(1)
Input
0dBFS Input
+25°C
+25°C
400
65
1.25 || 4
TTL/HCT Compatible CMOS
Falling Edge
f
S
= 2.5MHz
+25°C
Full
∆
+V
S
=
±5%
∆
+V
S
=
±5%
+25°C
Full
+25°C
10k
6.5
±0.4
±0.6
±95
0.01
±2.6
0.02
±1.5
±2.5
0.15
±3.5
0.15
40M
%
%
ppm/°C
%FSR/%
%
%FSR/%
Sample/s
Convert Cycle
TYP
12
+70
+85
+3.25
MAX
UNITS
Bits
°C
°C
V
V
MHz
MHz
MΩ || pF
Start Conversion
t
H
= 13ns
(3)
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
65
60
58
55
±0.6
±0.8
±0.4
±0.5
Tested
±1.9
72
66
61
61
±1.0
±1.0
LSB
LSB
LSB
LSB
LSB
LSB
dBFS
dBFS
dBFS
dBFS
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure
DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope
signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
2
ADS800
www.ti.com
SBAS035B
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= +25°C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS800U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
(Cont.)
2-Tone Intermodulation Distortion (IMD)
(4)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Aperture Delay Time
Aperture Jitter
Over-Voltage Recovery Time
(5)
OUTPUTS
Logic Family
Logic Coding
Logic Levels
NTSC or PAL
NTSC or PAL
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
61
57
61
56
59
54
56
51
–63
–62
64
63
62
62
63
64
58
57
0.5
0.1
2
7
2
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
%
degrees
ns
ps rms
ns
1.5x Full-Scale Input
Logic “LO”,
C
L
= 15pF max
Logic “HI”,
C
L
= 15pF max
Logic Selectable
Full
Full
TTL/HCT Compatible CMOS
SOB or BTC
0
0.4
+2.5
20
2
+4.75
+5.0
78
78
390
390
75
+V
S
40
10
+5.25
93
97
465
485
V
V
ns
ns
V
mA
mA
mW
mW
°C/W
3-State Enable Time
3-State Disable Time
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Supply Current: +I
S
Power Consumption
Thermal Resistance,
θ
JA
SO-28
Operating
Operating
Operating
Operating
Operating
Full
Full
+25°C
Full
+25°C
Full
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure
DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope
signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
ADS800
SBAS035B
www.ti.com
3
PIN CONFIGURATION
Top View
SO
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DESIGNATOR
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
+V
S
CLK
+V
S
OE
MSBI
DESCRIPTION
Ground
Bit 1, Most Significant Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12, Least Significant Bit
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
HI: High Impedance State. LO or Floating: Nor-
mal Operation. Internal pull-down resistors.
Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight
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