5962R9957301QYC datasheet, PDF

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5962R9957301QYC: DescriptionField Programmable Gate Array, 661111 Gates, 15552-Cell, CMOS, CQFP228, QFP-228; CategoryProgrammable logic devices Programmable logic; File Size604KB，17 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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5962R9957301QYC Overview

Field Programmable Gate Array, 661111 Gates, 15552-Cell, CMOS, CQFP228, QFP-228

5962R9957301QYC Parametric

Parameter Name	Attribute value
Maker	XILINX
Parts packaging code	QFP
package instruction	GQFF, TPAK228,2.5SQ,25
Contacts	228
Reach Compliance Code	compliant
ECCN code	9A515.E.2
Combined latency of CLB-Max	0.8 ns
JESD-30 code	S-CQFP-F228
JESD-609 code	e4
length	39.37 mm
Configurable number of logic blocks	3456
Equivalent number of gates	661111
Number of entries	162
Number of logical units	15552
Output times	162
Number of terminals	228
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	661111 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF
Encapsulate equivalent code	TPAK228,2.5SQ,25
Package shape	SQUARE
Package form	FLATPACK, GUARD RING
power supply	1.2/3.6,2.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	3.0226 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	FLAT
Terminal pitch	0.635 mm
Terminal location	QUAD
total dose	100k Rad(Si) V
width	39.37 mm

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QPro Virtex 2.5V Radiation-Hardened FPGAs

DS028 (v2.1) November 5, 2010

Product Specification

Features

•

0.22 µm 5-layer epitaxial process

QML certified

Radiation-hardened FPGAs for space and satellite

applications

Guaranteed total ionizing dose to 100K Rad(si)

Latch-up immune to LET = 125 MeV cm

/mg

SEU immunity achievable with recommended

redundancy implementation

Guaranteed over the full military temperature range

(–55°C to +125°C)

Fast, high-density Field-Programmable Gate Arrays

•

Densities from 100k to 1M system gates

System performance up to 200 MHz

Hot-swappable for Compact PCI

16 high-performance interface standards

Connects directly to ZBTRAM devices

Four dedicated delay-locked loops (DLLs) for

advanced clock control

Four primary low-skew global clock distribution

nets, plus 24 secondary global nets

LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

Configurable synchronous dual-ported 4k-bit

RAMs

Fast interfaces to external high-performance RAMs

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

Internal 3-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensing device

•

Supported by FPGA Foundation™ and Alliance

Development Systems

•

Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

Wide selection of PC and workstation platforms

Unlimited reprogrammability

Four programming modes

SRAM-based in-system configuration

Available to Standard Microcircuit Drawings. Contact

Defense Supply Center Columbus (DSCC) for more

information at

http://www.dscc.dla.mil

•

5962-99572 for XQVR300

5962-99573 for XQVR600

5962-99574 for XQVR1000

Multi-standard SelectIO™ interfaces

Description

The QPro™ Virtex® family delivers high-performance,

high-capacity programmable logic solutions. Dramatic

increases in silicon efficiency result from optimizing the new

architecture for place-and-route efficiency and exploiting an

aggressive 5-layer-metal 0.22 µm CMOS process. These

advances make QPro Virtex FPGAs powerful and flexible

alternatives to mask-programmed gate arrays. The Virtex

radiation-hardened family comprises the three members

shown in

Table 1.

Building on experience gained from previous generations of

FPGAs, the Virtex family represents a revolutionary step

forward in programmable logic design. Combining a wide

variety of programmable system features, a rich hierarchy of

fast, flexible interconnect resources, and advanced process

technology, the QPro Virtex family delivers a high-speed

and high-capacity programmable logic solution that

enhances design flexibility while reducing time-to-market.

Refer to the Virtex 2.5V FPGA commercial data sheet at

http://www.xilinx.com/support/documentation/virtex.htm

for

more information on device architecture and timing

specifications.

Built-in clock-management circuitry

Hierarchical memory system

•

Flexible architecture that balances speed and density

•

other countries. All other trademarks are the property of their respective owners.

DS028 (v2.1) November 5, 2010

Product Specification

www.xilinx.com

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