P3P623S05A/B,
P3P623S09A/B
Timing-Safet Peak EMI
Reduction IC
Functional Description
P3P623S05/09 is a versatile, 3.3 V Zero−delay buffer
designed to distribute Timing−Safe clocks with Peak EMI
reduction. P3P623S05 is an eight−pin version, accepts one
reference input and drives out five low−skew Timing−Safe
clocks. P3P623S09 accepts one reference input and drives
out nine low−skew Timing−Safe clocks.
All parts have on−chip PLL that locks to an input clock on
the CLKIN pin. The PLL feedback is on−chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple P3P623S05 / P3P623S09 devices can accept the
same input clock and distribute it. In this case, the skew
between the outputs of the two devices is guaranteed to be
less than 700 pS.
All outputs have less than 200 pS of cycle−to−cycle jitter.
The input and output propagation delay is guaranteed to be
less than
±350
pS, and the output−to−output skew is
guaranteed to be less than 250 pS.
Refer “Spread Spectrum Control and Input−Output Skew
Table” for deviations and Input−Output Skew for
P3P623S05A/B and P3P623S09A/B devices.
P3P623S05/09 operates from a 3.3 V supply and is
available in TSSOP package, as shown in the ordering
information table.
Application
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TSSOP8 4.4x3
CASE 948AL
TSSOP16 4.4x5
CASE 948AN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Spread Spectrum Frequency Generation
P3P623S05/09 is targeted for use in Displays and memory
interface systems.
General Features
•
Clock Distribution with Timing−Safe Peak EMI
•
•
•
•
•
•
Reduction
Input Frequency Range: 20 MHz
−
50 MHz
Multiple Low Skew Timing−Safe Outputs:
♦
P3P623S05: 5 Outputs
♦
P3P623S09: 9 Outputs
Supply Voltage: 3.3 V
±
0.3 V
Packaging Information:
♦
P3P623S05: 8 Pin TSSOP
♦
P3P623S09: 16 Pin TSSOP
True Drop−in Solution for Zero Delay Buffer
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The P3P623S05/09 uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
©
Semiconductor Components Industries, LLC, 2014
October, 2014
−
Rev. 0
1
Publication Order Number:
P3P623S05B/D
P3P623S05A/B, P3P623S09A/B
BLOCK DIAGRAM
PLL
CLKIN
CLKOUT
CLK1
CLK2
CLK3
PLL
CLKIN
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
P3P623S05A/B
CLK4
S2
S1
Select Input
Decoding
CLKB1
CLKB2
CLKB3
P3P623S09A/B
CLKB4
Figure 1. General Block Diagram
PIN CONFIGURATION
CLKIN
CLK1
CLK2
GND
1
2
8
7
CLKOUT
CLK4
VDD
CLK3
P3P623S05A/B
3
4
6
5
Figure 2. Pin Configuration for P3P623S05A/B
Table 1. PIN DESCRIPTION FOR P3P623S05A/B
Pin #
1
2
3
4
5
6
7
8
Pin Name
CLKIN (Note 1)
CLK1 (Note 2)
CLK2 (Note 2)
GND
CLK3 (Note 2)
VDD
CLK4 (Note 2)
CLKOUT (Note 3)
Type
I
O
O
P
O
P
O
O
Description
External reference Clock input, 5 V tolerant input.
Buffered clock output (Note 3)
Buffered clock output (Note 3)
Ground
Buffered clock output (Note 3)
3.3 V supply
Buffered clock output (Note 3)
Buffered clock output. Internal feedback on this pin.
1. Weak pull−down
2. Weak pull−down on all outputs
3. Buffered clock output is Timing−Safe
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P3P623S05A/B, P3P623S09A/B
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
16
CLKOUT
15
CLKA4
14
CLKA3
13
VDD
P3P623S09A/B
5
6
7
8
12
GND
11
CLKB4
10
CLKB3
9
S1
Figure 3. Pin Configuration for P3P623S09A/B
Table 2. PIN DESCRIPTION FOR P3P623S05A/B
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1.
2.
3.
4.
Pin Name
CLKIN (Note 1)
CLKA1 (Note 2)
CLKA2 (Note 2)
VDD
GND
CLKB1 (Note 2)
CLKB2 (Note 2)
S2 (Note 3)
S1 (Note 3)
CLKB3 (Note 2)
CLKB4 (Note 2)
GND
VDD
CLKA3 (Note 2)
CLKA4 (Note 2)
CLKOUT (Note 2)
Type
I
O
O
P
P
O
O
I
I
O
O
P
P
O
O
O
Description
External reference Clock input, 5 V tolerant input.
Buffered clock Bank A output (Note 4)
Buffered clock Bank A output (Note 4)
3.3 V supply
Ground
Buffered clock Bank B output (Note 4)
Buffered clock Bank B output (Note 4)
Select input, bit 2. See Select Input Decoding table for P3P623S09A/B for more details.
Select input, bit 1. See Select Input Decoding table for P3P623S09A/B for more details.
Buffered clock Bank B output (Note 4)
Buffered clock Bank B output (Note 4)
Ground
3.3 V supply
Buffered clock Bank A output (Note 4)
Buffered clock Bank A output (Note 4)
Buffered clock output. Internal feedback on this pin.
Weak pull−down
Weak pull−down on all outputs
Weak pull−up on these inputs
Buffered clock output is Timing−Safe
Table 3. SELECT INPUT DECODING TABLE FOR P3P623S09A/B
S2
0
0
1
1
S1
0
1
0
1
CLK A1
−
A4
Three−state
Driven
Driven
Driven
CLK B1
−
B4
Three−state
Three−state
Driven
Driven
CLKOUT
(Note 5)
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut−Down
N
N
Y
N
5. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the Output.
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P3P623S05A/B, P3P623S09A/B
Table 4. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW TABLE
Frequency (MHz)
32
Device
P3P623S05A / 09A
P3P623S05B / 09B
NOTE: T
SKEW
is measured in units of the Clock Period
Deviation
±0.25%
±0.50%
Input−Output Skew (+T
SKEW
)
0.125
0.25
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VIN
T
STG
T
s
T
J
T
DV
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (CLKIN)
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−0.5
to +7
−65
to +125
260
150
2
°C
°C
°C
KV
Unit
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 6. OPERATING CONDITIONS
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
−40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
Table 7. ELECTRICAL CHARACTERISTICS
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
O
Description
Input LOW Voltage (Note 1)
Input HIGH Voltage (Note 1)
Input LOW Current
Input HIGH Current
Output LOW Voltage (Note 2)
Output HIGH Voltage (Note 2)
Supply Current
Output Impedance
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA
I
OH
=
−8
mA
Unloaded outputs
2.4
15
23
2.0
50
100
0.4
Test Conditions
Min
Typ
Max
0.8
Units
V
V
mA
mA
V
V
mA
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. CLKIN input has a threshold voltage of VDD/2
2. Parameter is guaranteed by design and characterization. Not tested in production.
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P3P623S05A/B, P3P623S09A/B
Table 8. SWITCHING CHARACTERISTICS
Parameter
Description
Input Frequency
1/t
1
t
D
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Output Frequency
Duty Cycle (Notes 3, 4) = (t
2
/t
1
) * 100
Output Rise Time (Notes 3, 4)
Output Fall Time (Notes 3, 4)
Output−to−output skew (Notes 3, 4)
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 4)
Device−to−Device Skew (Note 4)
Cycle−to−cycle jitter (Notes 3, 4)
PLL Lock Time (Note 4)
30 pF load
Measured at V
DD
/2
Measured between 0.8 V and 2.0 V
Measured between 2.0 V and 0.8 V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the
CLKOUT pins of the device
Loaded outputs
Stable power supply, valid clock
presented on CLKIN pin
Test Conditions
Min
20
20
40
50
Typ
Max
50
50
60
2.5
2.5
250
±350
700
±200
1.0
Units
MHz
MHz
%
nS
nS
pS
pS
pS
pS
mS
3. All parameters specified with 30 pF loaded outputs.
4. Parameter is guaranteed by design and characterization. Not tested in production.
Switching Waveforms
t
1
t
2
V
DD
/2
OUTPUT
V
DD
/2
V
DD
/2
Figure 4. Duty Cycle Timing
2V
0.8V
2V
0.8V
OUTPUT
t
3
t
4
Figure 5. All Outputs Rise/Fall Time
V
DD
/2
OUTPUT
V
DD
/2
OUTPUT
t5
Figure 6. Output−Output Skew
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