ESD/EMI Protection
for Color LCD Interfaces
PROTECTION PRODUCTS - EMIClamp
TM
Description
The EClamp
TM
2384K is a low pass filter array with
integrated TVS diodes. It is designed to suppress un-
wanted EMI/RFI signals and provide electrostatic dis-
charge (ESD) protection in portable electronic equip-
ment. This state-of-the-art device utilizes solid-state
silicon-avalanche technology for superior clamping
performance and DC electrical characteristics. It has
been optimized for protection of color LCD panels
in cellular phones and other portable electronics.
The device consists of four identical circuits comprised
of TVS diodes for ESD protection, and a resistor -
capacitor network for EMI/RFI filtering. A series
resistor value of 200Ω and a capacitance value of 12pF
are used to achieve 30dB minimum attenuation from
800MHz to 2.7GHz. The TVS diodes provide effective
suppression of ESD voltages in excess of ±15kV (air
discharge) and ±8kV (contact discharge) per IEC 61000-
4-2, level 4.
The EClamp2384K is in a 8-pin, RoHS/WEEE compliant,
SLP1713P8 package. It measures 1.7 x 1.3 x 0.50mm.
The leads are spaced at a pitch of 0.4mm and are
finished with lead-free NiPdAu. The small package
makes it ideal for use in portable electronics such as
cell phones, digital still cameras, and PDAs.
EClamp2384K
PRELIMINARY
Features
Bidirectional EMI/RFI filter with integrated TVS
for ESD protection
ESD protection to
IEC 61000-4-2 (ESD) Level 4,
±15kV (air), ±8kV (contact)
Filter performance: 30dB minimum attenuation
800MHz to 2.7GHz
TVS working voltage: 5V
Resistor: 200Ω
+/− 15%
Typical Capacitance: 12pF (VR = 2.5V)
Protection and filtering for four lines
Solid-state technology
Mechanical Characteristics
SLP1713P8 8-pin package
RoHS/WEEE Compliant
Nominal Dimensions: 1.7 x 1.3 x 0.50 mm
Lead Pitch: 0.40mm
Lead finish: NiPdAu
Marking: Marking Code
Packaging: Tape and Reel per EIA 481
Applications
Color LCD Protection
Cell Phone CCD Camera Lines
Clamshell Cell Phones
Circuit Diagram (Each Line)
Package Configuration
1.70
1 2
200
Ω
IN
12pF
12pF
OUT
1.30
0.40 BSC
GND
0.50
Device Schematic (4X)
Revision 11/15/2007
8 Pin SLP package (Bottom Side View)
Nominal Dimensions in mm
1
www.semtech.com
EClamp2384K
PROTECTION PRODUCTS
Maximum Ratings
R ating
ESD p er IEC 61000-4-2 (Air)
ESD p er IEC 61000-4-2 (Contact)
Junction Temp erature
Op erating Temp erature
Storage Temp erature
Symbol
V
ESD
T
J
T
op
T
STG
Value
+/- 17
+/- 12
125
-40 to +85
-55 to +150
PRELIMINARY
Units
kV
o
C
C
C
o
o
Electrical Characteristics (T = 25
o
C)
P a r a met er
T VS Reverse Stand-Of f Voltage
T VS Reverse Breakdown Voltage
T VS Reverse Leakage Current
Total Series Resistance
Capacitance
Total Capacitance
Symb ol
V
RWM
V
BR
I
R
R
C
1,
C
2
C
in
C on d i t i on s
Mi n i mu m
Ty p i c a l
M a xi m u m
5
Un i ts
V
V
μ
A
Ohms
pF
pF
I
t
= 1mA
V
RWM
= 3.0V
Each Line
Each Line
V
R
= 2.5V, f = 1MHz
Input to Gnd,
Each Line
V
R
= 2.5V, f = 1MHz
6
8
10
0.5
170
10
20
200
12
24
230
15
30
©
2007 Semtech Corp.
2
www.semtech.com
EClamp2384K
PROTECTION PRODUCTS
Typical Characteristics
Typical Insertion Loss S21 (Each Line)
CH1 S21
LOG
6 dB / REF 0 dB
1: -12.305 dB
106.6 MHz
2: -35.996 dB
800 MHz
3: -38.349 dB
1.8 GHz
1
PRELIMINARY
Analog Crosstalk (Each Line)
CH1 S21
LOG
20 dB /REF 0 dB
0 dB
-6 dB
-12 dB
-18 dB
-24 dB
-30 dB
-36 dB
2
4
3
4: -36.250 dB
2.7 GHz
-42 dB
-48 dB
1
MHz
START . 030 MHz
10
MHz
100
MHz
3
1
GHz GHz
STOP 3000. 000000 MHz
START. 030 MHz
.
STOP 3000 000000 MHz
ESD Clamping (+8kV Contact)
ESD Clamping (-8kV Contact)
Note: Data is taken with a 10x attenuator
Note: Data is taken with a 10x attenuator
Normalized Capacitance vs. Reverse Voltage
(Normalized to 2.5 volts)
2
1.5
C
J
(V
R
) / C
J
(V
R
=2.5)
1
0.5
f = 1 MHz
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Reverse Voltage - V
R
(V)
©
2007 Semtech Corp.
3
www.semtech.com
EClamp2384K
PROTECTION PRODUCTS
Device Connection
The EClamp2384K is comprised of four identical
circuits each consisting of a low pass filter for EMI/RFI
suppression and dual TVS diodes for ESD protection.
The device is in a 8-pin SLP package. Electrical con-
nection is made to the 8 pins located at the bottom of
the device. A center tab serves as the ground connec-
tion. The device has a flow through design for easy
layout. Pin connections are noted in Figure 1. All path
lengths should be kept as short as possible to minimize
the effects of parasitic inductance in the board traces.
Recommendations for the ground connection are given
below.
Ground Connection Recommendation
Parasitic inductance present in the board layout will
affect the filtering performance of the device. As
frequency increases, the effect of the inductance
becomes more dominant. This effect is given by
Equation 1.
Equation 1: The Impedance of an Inductor at
Frequency XLF
PRELIMINARY
Figure 1 - Pin Identification and Configuration
(Top Side View)
In 1
In 2
In 3
In 4
1
8
Gnd
4
5
Out 1
Out 2
Out 3
Out 4
Pin
1-4
5-8
Center Tab
Identification
Inp ut Lines
Outp ut Lines
Ground
XLF(L, f )
=
2 *
π
* f * L
Where:
L= Inductance (H)
f = Frequency (Hz)
Via connections to the ground plane form rectangular
wire loops or ground loop inductance as shown in
Figure 2. Ground loop inductance can be reduced by
using multiple vias to make the connection to the
ground plane. Bringing the ground plane closer to the
signal layer (preferably the next layer) also reduces
ground loop inductance. Multiple vias in the device
ground pad will result in a lower inductive ground loop
over two exterior vias. Vias with a diameter d are
separated by a distance y run between layers sepa-
rated by a distance x. The inductance of the loop path
is given by Equation 2. Thus, decreasing distance x
and y will reduce the loop inductance and result in
better high frequency filter characteristics.
Figure 2 - Inductance of Rectangular Wire Loops
Ground
Via 1
Ground
Via 2
d
x
Signal Layer
y
Ground Layer
Layer
Equation 2: Inductance of Rectangular Wire Loop
LRECT(d, x , y)
=
10.16 *10
−
9
* x * ln
Where:
d = Diameter of the wire (in)
x = Length of wire loop (in)
y = Breath of wire loop (in)
[
[ ]
+
y * ln
[ ]
]
2*y
d
2*x
d
©
2007 Semtech Corp.
4
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EClamp2384K
PROTECTION PRODUCTS
Applications Information
Figure 3 shows the recommended device layout. The
ground pad vias have a diameter of 0.008 inches (0.20
mm) while the two external vias have a diameter of
0.010 inches (0.250mm). The internal vias are spaced
approximately evenly from the center of the pad. The
designer may choose to use more vias with a smaller
diameter (such as 0.005 inches or 0.125mm) since
changing the diameter of the via will result in little
change in inductance (i.e. the log function in Equation 2
in highly insensitive to parameter d) . Figure 4 shows a
typical insertion loss (S21) plot for the device using
Semtech’s filter evaluation board with 50 Ohm traces
and the recommended via configuration.
PRELIMINARY
Figure 4 - Filter Characteristics Using Recommended
Layout with Internal Vias
CH1 S21
LOG
6 dB / REF 0 dB
1: -12.305 dB
106.6 MHz
2: -35.996 dB
800 MHz
3: -38.349 dB
1.8 GHz
1
0 dB
-6 dB
-12 dB
-18 dB
-24 dB
-30 dB
-36 dB
2
4
3
4: -36.250 dB
2.7 GHz
-42 dB
Figure 3 - Recommended Layout Using Ground Vias
-48 dB
1
MHz
START . 030 MHz
10
MHz
100
MHz
3
1
GHz GHz
STOP 3 000. 000000 MHz
©
2007 Semtech Corp.
5
www.semtech.com
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