MT9D436M-5X datasheet, PDF - EEWORLD Datasheet

OBSOLETE

4, 8 MEG x 36

ECC-OPTIMIZED DRAM SIMMs

DRAM

MODULE

FEATURES

• Four-CAS#, ECC-optimized configuration in a 72-pin,

single in-line memory module (SIMM)

• 16MB (4 Meg x 36) and 32MB (8 Meg x 36)

• High-performance CMOS silicon-gate process

• Single 5V

±10%

power supply

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

• 2,048-cycle refresh distributed across 32ms

• Extended Data-Out (EDO) PAGE MODE access

MT9D436 X

MT18D836 X

For the latest data sheet revisions, please refer to the Micron

Web site: www.micron.com/mti/msp/html/datasheet.html

PIN ASSIGNMENT (Front View)

72-Pin SIMM

4 Meg x 36 (shown)

8 Meg x 36

1

36

37

72

OPTIONS

• Timing

50ns access

60ns access

• Package

72 -pin SIMM

MARKING

-5

-6

M

KEY TIMING PARAMETERS

SPEED

-5

-6

t

RC

t

RAC

t

PC

t

AA

t

CAC

t

CAS

84ns

104ns

50ns

60ns

20ns

25ns

30ns

13ns

15ns

8ns

10ns

PART NUMBERS

PART NUMBER

MT9D436M-x X

MT18D836M-x X

x = speed

CONFIGURATION

4 Meg x 36

8 Meg x 36

FEATURES

4 CAS#, ECC

MODE

EDO

PIN SYMBOL

1

V

SS

19

A10

37

DQ18

55

DQ13

2

DQ1

20

DQ5

38

DQ36

56

DQ31

3

DQ19

21

DQ23

39

V

SS

57

DQ14

4

DQ2

22

DQ6

40

CAS0#

58

DQ32

5

DQ20

23

DQ24

41

CAS2#

59

V

DD

6

DQ3

24

DQ7

42

CAS3#

60

DQ33

7

DQ21

25

DQ25

43

CAS1#

61

DQ15

8

DQ4

26

DQ8

44

RAS0#

62

DQ34

9

DQ22

27

DQ26

45 NC/RAS1#* 63

DQ16

10

V

DD

28

A7

46

NC

64

DQ35

11

NC

29

NC (A11)

47

WE#

65

DQ17

12

A0

30

V

DD

48

NC

66

NC

13

A1

31

A8

49

DQ10

67

PRD1

14

A2

32

A9

50

DQ28

68

PRD2

15

A3

33 NC/RAS3#* 51

DQ11

69

PRD3

16

A4

34

RAS2#

52

DQ29

70

PRD4

17

A5

35

DQ27

53

DQ12

71

NC

18

A6

36

DQ9

54

DQ30

72

V

SS

*32MB version only

NOTE:

Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

GENERAL DESCRIPTION

The MT9D436 X and MT18D836 X are randomly ac-

cessed, 16MB and 32MB solid-state memories organized in

a x36 configuration. These modules are designed for sys-

tems that utilize ECC and do not conduct single-byte ac-

cesses. These modules do not support parity functionality.

During READ or WRITE cycles, each bit is uniquely

addressed through 20 address bits that are entered 10 bits

(A0 -A9) at a time. RAS# is used to latch the first 10 bits and

CAS# the latter 10 bits. READ or WRITE cycles are selected

with the WE# input. A logic HIGH on WE# dictates read

mode, while a logic LOW on WE# dictates write mode.

During a WRITE cycle, data-in (D) is latched by the falling

edge of WE# or CAS#, whichever occurs last. EARLY WRITE

4, 8 Meg x 36 ECC-Optimized DRAM SIMMs

DM65.p65 – Rev. 9/98

occurs when WE# goes LOW prior to CAS# going LOW,

and the output pin(s) remain open (High-Z) until the next

CAS# cycle.

EDO PAGE MODE

EDO PAGE MODE is an accelerated FAST-PAGE-MODE

cycle. The primary advantage of EDO is the availability of

data-out even after CAS# goes back HIGH. EDO provides

for CAS# precharge time (

t

CP) to occur without the output

data going invalid. This elimination of CAS# output control

provides for pipelined READs.

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of

CAS#. EDO operates like FAST-PAGE-MODE READs, ex-

cept data will be held valid or become valid after CAS# goes

1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

Micron is a registered trademark of Micron Technology, Inc.

OBSOLETE

4, 8 MEG x 36

ECC-OPTIMIZED DRAM SIMMs

EDO PAGE MODE (continued)

HIGH, as long as RAS# is held LOW. (Refer to the

MT4C4M4E8 DRAM data sheet for additional information

on EDO functionality.)

the RAS# HIGH time. Memory cell data is retained in its

correct state by maintaining power and executing any

RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#

ONLY, CBR or HIDDEN) so that all 2,048 combinations of

RAS# addresses are executed at least every 32ms, regard-

less of sequence. The CBR REFRESH cycle will invoke the

refresh counter for automatic RAS# addressing.

REFRESH

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.

Also, the chip is preconditioned for the next cycle during

JEDEC-DEFINED

PRESENCE-DETECT – MT9D436 (16MB)

SYMBOL

PRD1

PRD2

PRD3

PRD4

67

68

69

70

-5

Vss

NC

Vss

-6

Vss

NC

JEDEC-DEFINED

PRESENCE-DETECT – MT18D836 (32MB)

SYMBOL

PRD1

PRD2

PRD3

PRD4

67

68

69

70

-5

NC

Vss

-6

NC

Vss

NC

4, 8 Meg x 36 ECC-Optimized DRAM SIMMs

DM65.p65 – Rev. 9/98

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

OBSOLETE

4, 8 MEG x 36

ECC-OPTIMIZED DRAM SIMMs

FUNCTIONAL BLOCK DIAGRAM

MT9D436 (16MB)

DQ1

DQ8

DQ9, 18, 27, 36

DQ10

DQ17

DQ1 - 4

WE#

U1

CAS0#

RAS0#

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U2

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U5

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U3

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U4

CAS#

RAS#

OE# A0–A10

11

CAS1#

WE#

11

DQ19

DQ26

DQ28

DQ35

DQ1 - 4

WE#

U6

CAS2#

RAS2#

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U7

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U3

U8

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U9

CAS#

RAS#

OE# A0–A10

CAS3#

A0–A10

11

V

DD

V

SS

U1-U9

U1-U9 = 4 Meg x 4 DRAMs

4, 8 Meg x 36 ECC-Optimized DRAM SIMMs

DM65.p65 – Rev. 9/98

3

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

OBSOLETE

4, 8 MEG x 36

ECC-OPTIMIZED DRAM SIMMs

FUNCTIONAL BLOCK DIAGRAM

MT18D836 (32MB)

DQ1

DQ8

DQ9, 18, 27, 36

DQ10

DQ17

DQ1 - 4

WE#

U1

CAS0#

RAS0#

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U2

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U5

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U3

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U4

CAS#

RAS#

OE# A0–A10

CAS1#

WE#

11

DQ19

DQ26

DQ28

DQ35

DQ1 - 4

WE#

U6

CAS2#

RAS2#

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U7

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U8

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U9

CAS#

RAS#

OE# A0–A10

CAS3#

A0–A10

11

DQ1

DQ8

DQ9, 18, 27, 36

DQ10

DQ17

DQ1 - 4

WE#

U10

CAS#

RAS1#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U11

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U14

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U12

CAS#

RAS#

OE# A0–A10

DQ1 - 4

WE#

U13

CAS#

RAS#

OE# A0–A10

11

DQ19

DQ26

DQ28

DQ35

DQ1 - 4

WE#

CAS# U15

RAS3#

RAS#

OE# A0–A10

DQ1 - 4

WE#

CAS# U16

RAS#

OE# A0–A10

DQ1 - 4

WE#

CAS# U17

RAS#

OE# A0–A10

DQ1 - 4

WE#

CAS# U18

RAS#

OE# A0–A10

11

V

DD

V

SS

U1-U18

U1-U18 = 4 Meg x 4 DRAMs

4, 8 Meg x 36 ECC-Optimized DRAM SIMMs

DM65.p65 – Rev. 9/98

4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

OBSOLETE

4, 8 MEG x 36

ECC-OPTIMIZED DRAM SIMMs

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

DD

Supply Relative to V

SS

............. -1V to +7V

Operating Temperature, T

A

(ambient) .......... 0°C to +70°C

Storage Temperature (plastic) .................... -55°C to +125°C

Power Dissipation ............................................................. 9W

Short Circuit Output Current ..................................... 50mA

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only, and functional operation of the

device at these or any other conditions above those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6) (V

DD

= +5V

±10%)

PARAMETER/CONDITION

SUPPLY VOLTAGE

INPUT HIGH VOLTAGE: Logic 1; All inputs

INPUT LOW VOLTAGE: Logic 0; All inputs

INPUT LEAKAGE CURRENT:

Any input 0V

≤

V

IN

≤

5.5V

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT:

(DQ is disabled; 0V

≤

V

OUT

≤

5.5V)

OUTPUT LEVELS:

Output High Voltage (I

OUT

= -5mA)

Output Low Voltage (I

OUT

= 4.2mA)

CAS0#-CAS3#

A0-A10, WE#

RAS0#-RAS3#

DQ1-DQ36

SYMBOL

V

DD

V

IH

V

IL

I

1

I

2

I

3

I

OZ

V

OH

V

OL

MIN

4.5

2.4

-1.0

-12

-36

-10

2.4

–

MAX

5.5

V

DD

+ 1

0.8

12

36

10

–

0.4

UNITS

V

µA

V

22

NOTES

Icc SPECIFICATIONS AND CONDITIONS

(Notes: 1, 5, 6) (V

DD

= +5V

±10%)

PARAMETER/CONDITION

STANDBY CURRENT: (TTL)

(RAS# = CAS# = V

IH

)

STANDBY CURRENT: (CMOS)

(RAS# = CAS# = Other Inputs = V

DD

- 0.2V)

OPERATING CURRENT: Random READ/WRITE

Average power supply current

(RAS#, CAS#, address cycling:

t

RC =

t

RC [MIN])

OPERATING CURRENT: EDO PAGE MODE

Average power supply current

(RAS# = V

IL

, CAS#, address cycling:

t

PC =

t

PC [MIN])

REFRESH CURRENT: RAS#-ONLY

Average power supply current

(RAS# cycling, CAS# = V

IH

:

t

RC =

t

RC [MIN])

REFRESH CURRENT: CBR

Average power supply current

(RAS#, CAS#, address cycling;

t

RC =

t

RC [MIN])

SYMBOL

I

CC

1

I

CC

2

SIZE

16MB

32MB

16MB

32MB

16MB

32MB

16MB

32MB

16MB

32MB

16MB

32MB

-5

9

18

5

9

1,260

1,269

990

999

1,260

1,269

1,260

1,269

MAX

-6

9

18

5

9

1,170

1,179

900

909

1,170

1,179

1,170

1,179

UNITS

mA

3, 21

NOTES

I

CC

3

I

CC

4

mA

3, 21

I

CC

5

mA

3, 21

I

CC

6

mA

3, 4

4, 8 Meg x 36 ECC-Optimized DRAM SIMMs

DM65.p65 – Rev. 9/98

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	SIMM
package instruction	SIMM-72
Contacts	72
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FAST PAGE WITH EDO
Maximum access time	50 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O type	COMMON
JESD-30 code	R-XSMA-N72
memory density	150994944 bit
Memory IC Type	EDO DRAM MODULE
memory width	36
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	72
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX36
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	SIMM
Encapsulate equivalent code	SSIM72
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
refresh cycle	2048
Maximum standby current	0.024 A
Maximum slew rate	0.99 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	SINGLE
Maximum time at peak reflow temperature	NOT SPECIFIED

	MT9D436M-5X	MT9D436M-6X
Description	EDO DRAM Module, 4MX36, 50ns, CMOS, SIMM-72	EDO DRAM Module, 4MX36, 60ns, CMOS, SIMM-72
Is it Rohs certified?	incompatible	incompatible
Maker	Micron Technology	Micron Technology
Parts packaging code	SIMM	SIMM
package instruction	SIMM-72	SIMM-72
Contacts	72	72
Reach Compliance Code	unknown	unknow
ECCN code	EAR99	EAR99
access mode	FAST PAGE WITH EDO	FAST PAGE WITH EDO
Maximum access time	50 ns	60 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O type	COMMON	COMMON
JESD-30 code	R-XSMA-N72	R-XSMA-N72
memory density	150994944 bit	150994944 bi
Memory IC Type	EDO DRAM MODULE	EDO DRAM MODULE
memory width	36	36
Humidity sensitivity level	1	1
Number of functions	1	1
Number of ports	1	1
Number of terminals	72	72
word count	4194304 words	4194304 words
character code	4000000	4000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C
organize	4MX36	4MX36
Output characteristics	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	SIMM	SIMM
Encapsulate equivalent code	SSIM72	SSIM72
Package shape	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225	225
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
refresh cycle	2048	2048
Maximum standby current	0.024 A	0.024 A
Maximum slew rate	0.99 mA	1.08 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm
Terminal location	SINGLE	SINGLE
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED

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