AD7451BRTZ-REEL7 datasheet, PDF

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AD7451BRTZ-REEL7: DescriptionIC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, ROHS COMPLIANT, MO-178BA, SOT-23, 8 PIN, Analog to Digital Converter; CategoryAnalog mixed-signal IC converter; File Size468KB，24 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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AD7451BRTZ-REEL7 Overview

IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, ROHS COMPLIANT, MO-178BA, SOT-23, 8 PIN, Analog to Digital Converter

AD7451BRTZ-REEL7 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ADI
Parts packaging code	SOIC
package instruction	ROHS COMPLIANT, MO-178BA, SOT-23, 8 PIN
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum analog input voltage	1.25 V
Minimum analog input voltage	-1.25 V
Maximum conversion time	16 µs
Converter type	ADC, SUCCESSIVE APPROXIMATION
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	2.9 mm
Maximum linear error (EL)	0.0244%
Number of analog input channels	1
Number of digits	12
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output bit code	BINARY
Output format	SERIAL
Package body material	PLASTIC/EPOXY
encapsulated code	LSSOP
Encapsulate equivalent code	TSSOP8,.1
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT APPLICABLE
power supply	3/5 V
Certification status	Not Qualified
Sampling rate	1 MHz
Sample and hold/Track and hold	TRACK
Maximum seat height	1.45 mm
Nominal supply voltage	3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT APPLICABLE
width	1.6 mm

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Pseudo Differential Input, 1 MSPS,

10- and 12-Bit ADCs in an 8-Lead SOT-23

AD7441/AD7451

FEATURES

Fast throughput rate: 1 MSPS

Specified for V

of 2.7 V to 5.25 V

Low power at max throughput rate:

4 mW max at 1 MSPS with V

= 3 V

9.25 mW max at 1 MSPS with V

= 5 V

Pseudo differential analog input

Wide input bandwidth:

70 dB SINAD at 100 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface:

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

Power-down mode: 1 µA max

8-lead SOT-23 and MSOP packages

FUNCTIONAL BLOCK DIAGRAM

IN+

T/H

IN–

REF

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

SCLK

AD7441/AD7451

SDATA

CONTROL LOGIC

03153-A-001

APPLICATIONS

Transducer interface

Battery-powered systems

Data acquisition systems

Portable instrumentation

GND

Figure 1.

GENERAL DESCRIPTION

The AD7441/AD7451

are, respectively, 10-bit and 12-bit high

speed, low power, successive approximation (SAR) analog-to-

digital converters that feature a pseudo differential analog input.

These parts operate from a single 2.7 V to 5.25 V power supply

and achieve very low power dissipation at high throughput rates

of up to 1 MSPS.

The AD7441/AD7451 contain a low noise, wide bandwidth,

differential track-and-hold (T/H) amplifier that handles input

frequencies up to 3.5 MHz. The reference voltage for these

devices is applied externally to the V

REF

pin and can range from

100 mV to V

, depending on the power supply and what suits

the application.

The conversion process and data acquisition are controlled

using CS and the serial clock, allowing the device to interface

with microprocessors or DSPs. The input signals are sampled

on the falling edge of CS when the conversion is initiated.

The SAR architecture of these parts ensures that there are no

pipeline delays.

PRODUCT HIGHLIGHTS

Operation with 2.7 V to 5.25 V power supplies.

High throughput with low power consumption. With a 3 V

supply, the AD7441/AD7451 offer 4 mW maximum power

consumption for a 1 MSPS throughput rate.

Pseudo differential analog input.

Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing

the power to be reduced as the conversion time is reduced

through the serial clock speed increase. These parts also

feature a shutdown mode to maximize power efficiency at

lower throughput rates.

Variable voltage reference input.

No pipeline delays.

Accurate control of the sampling instant via a CS input and

once-off conversion control.

ENOB > 10 bits typically with 500 mV reference.

Protected by U.S. Patent Number 6,681,332.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

www.analog.com

Tel: 781.329.4700

Fax: 781.326.8703

AD7441/AD7451

TABLE OF CONTENTS

AD7451 Specifications..................................................................... 3

AD7441 Specifications..................................................................... 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Terminology .................................................................................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 13

Circuit Information.................................................................... 13

Converter Operation.................................................................. 13

ADC Transfer Function............................................................. 13

Typical Connection Diagram ................................................... 14

Analog Input ............................................................................... 14

Analog Input Structure.............................................................. 14

Digital Inputs .............................................................................. 15

Reference ..................................................................................... 15

Serial Interface ............................................................................ 16

Modes of Operation ....................................................................... 18

Normal Mode.............................................................................. 18

Power-Down Mode.................................................................... 18

Power vs. Throughput Rate....................................................... 20

Microprocessor and DSP Interfacing ...................................... 20

Grounding and Layout Hints.................................................... 22

Evaluating Performance ............................................................ 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

REVISION HISTORY

2/05—Rev. A to Rev. B

Changes to Ordering Guide ...............................................................24

2/04—Rev. 0 to Rev. A

Updated Format.................................................................... Universal

Changes to General Description ....................................................... 1

Changes to Table 1 Footnotes ............................................................ 4

Changes to Table 2 Footnotes ............................................................ 6

Changes to Table 3 Footnotes ............................................................ 7

Changes to Table 5 .............................................................................. 9

Updated Figures 7, 8, and 9.............................................................. 13

Changes to Figure 23......................................................................... 16

Changes to Reference Section.......................................................... 17

Rev. B | Page 2 of 24

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