K4W1G1646D
1Gb gDDR3 SDRAM
1Gb gDDR3 SGRAM D-die
100 FBGA with Lead-Free & Halogen-Free
(RoHS Compliant)
CAUTION :
* This document includes some items still under discussion in JEDEC.
* Therefore, those may be changed without pre-notice based on JEDEC progress.
* And it’s highly recommended not to send the spec without Samsung’s permission.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K4W1G1646D
Revision History
Revision
0.0
0.1
0.2
Month
December
April
May
Year
2007
2008
2008
- First release
- gDDR3 1600/1800/2000 target AC parameter
History
1Gb gDDR3 SDRAM
- Correted typo table2.(tRC=44@2000Mbps) on page 3
- Corrected CWL=7 for gDDR3-1333 and CWL=8 for gDDR3-1600/1800/2000 on page 3
- Correted typo of table 48 and 49 on page 38
- Change 1600Mbps voltage from 1.5V to 1.8V
- Delete 2000Mbps speed bin
- Change tXP from 5 ns to 6ns at 1800Mbps
- Add
Precharge all Banks
command as item9 to Initialization sequence.
- Added current data(IDD) for 1600Mbps and 1800Mbps speed bin
- Added CL/ CWL values at gDDR3-1800 speed bin
- Added values of Thermal Characteristics
- Correction ball configuration on page 4.
- Correction AC parameter value(tRAS) typo
- Corrected tFAW value on page 42 was typo.
0.9
July
2008
1.0
1.1
1.2
1.3
September
October
December
February
2008
2008
2008
2009
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K4W1G1646D
1.0 Ordering Information
[ Table 1 ] Samsung gDDR3 ordering information table
Organization
64Mx16
gDDR3-1333 (9-9-9)
K4W1G1646D-EC15
gDDR3-1600 (11-11-11)
K4W1G1646D-EJ12
1Gb gDDR3 SDRAM
gDDR3-1800 (11-11-11)
K4W1G1646D-EJ11
Package
100 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. x16 Package
Part NO.
K4W1G1646D-EJ11
K4W1G1646D-EJ12
K4W1G1646D-EC15
Max Freq.
900MHz
800MHz
667MHz
Max Data Rate
1800Mbps/pin
1600Mbps/pin
1333Mbps/pin
V
DD
&V
DDQ
1.8V+0.1V
1.5V+0.075V
Package
100 Ball FBGA
2.0 Key Features
[ Table 2 ] 1Gb gDDR3 D-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
gDDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
gDDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
gDDR3-1800
11-11-11
1.1
11
12.1
12.1
34
46.1
Unit
ns
tCK
ns
ns
ns
ns
• V
DD
/V
DDQ
= 1.5V ± 0.075V at 1333
• V
DD
/V
DDQ
= 1.8V ± 0.1V at 1600 and 1800
• 667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin
900MHz f
CK
for 1800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10, 11
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) =7 (gDDR3-1333),
8 (gDDR3-1600), 8 (gDDDR3-1800),
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period : 7.8us at lower than T
CASE
85
°
C, 3.9us at
85
°
C < T
CASE
< 95
°
C
• Asynchronous Reset
• Package : 100 balls FBGA - x16 (with 4 support balls)
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-Free
The 1Gb gDDR3 SDRAM D-die is organized as a 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high speed double-data-
rate transfer rates of up to 1800Mb/sec/pin (gDDR3-1800) for general
applications.
The chip is designed to comply with the following key gDDR3 SDRAM
features such as posted CAS, Programmable CWL, Internal (Self) Calibra-
tion, On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The gDDR3 device operates
with a 1.5V ± 0.075V or 1.8V ± 0.1V power supply and 1.5V ± 0.075V or
1.8V ± 0.1V
DDQ
based upon operation frequency.
The 1Gb gDDR3 D-die device is available in 100ball FBGA(x16)
Note : The functionality described and the timing specifications included
in this data sheet are for the DLL Enabled mode of operation.
Note : 1.8V products haven’t backward compatibility with 1.5V products and vice versa.
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Rev. 1.3 February 2009
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