PM7329 S/UNI-APEX-LITE
DATASHEET
PMC-2010141
ATM TRAFFIC MANAGER AND SWITCH
PM7329
S
/UNI
-
APEX-LITE
TM
S/UNI-APEX-LITE
ATM/PACKET TRAFFIC MANAGER AND SWITCH
DATASHEET
ISSUE 1: FEBRUARY, 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM7329 S/UNI-APEX-LITE
DATASHEET
PMC-2010141
ATM TRAFFIC MANAGER AND SWITCH
REVISION HISTORY
Issue No.
Issue 1
Issue Date
February, 2001
Details of Change
Document created.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM7329 S/UNI-APEX-LITE
DATASHEET
PMC-2010141
ATM TRAFFIC MANAGER AND SWITCH
CONTENTS
1
2
3
4
5
6
7
8
9
DEFINITIONS
.......................................................................................... 1
FEATURES
.............................................................................................. 3
APPLICATIONS
....................................................................................... 7
REFERENCES.........................................................................................
8
APPLICATION EXAMPLES
..................................................................... 9
BLOCK DIAGRAM
................................................................................. 10
DESCRIPTION
...................................................................................... 12
PIN DIAGRAM
....................................................................................... 16
PIN DESCRIPTION................................................................................
17
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
LOOP ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE
INTERFACE (28 SIGNALS)
........................................................ 17
LOOP ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE
INTERFACE (34 SIGNALS)
........................................................ 22
WAN ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE
INTERFACE (25 SIGNALS)
........................................................ 26
WAN ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE
INTERFACE (25 SIGNALS)
........................................................ 31
CONTEXT MEMORY SYNCHRONOUS SSRAM INTERFACE (59
SIGNALS)....................................................................................
36
CELL BUFFER SDRAM INTERFACE (52 SIGNALS)
................. 38
MICROPROCESSOR INTERFACE (44 SIGNALS).....................
40
GENERAL (10 SIGNALS)
........................................................... 44
JTAG & SCAN INTERFACE (7 SIGNALS)
.................................. 45
POWER.......................................................................................
47
10
FUNCTIONAL DESCRIPTION
................................................................. 49
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
PM7329 S/UNI-APEX-LITE
DATASHEET
PMC-2010141
ATM TRAFFIC MANAGER AND SWITCH
10.1
ANY-PHY INTERFACES
............................................................. 49
10.1.1 RECEIVE INTERFACE.....................................................
49
10.1.2 TRANSMIT INTERFACE
.................................................. 51
10.2
10.3
10.4
10.5
10.6
10.7
10.8
LOOP PORT SCHEDULER
........................................................ 54
WAN PORT SCHEDULER
.......................................................... 55
WAN PORT ALIASING................................................................
57
WAN AND LOOP ICI SELECTION..............................................
58
MICROPROCESSOR INTERFACE
............................................ 58
MEMORY PORT
......................................................................... 62
SAR ASSIST
............................................................................... 63
10.8.1 TRANSMIT
....................................................................... 63
10.8.2 RECEIVE..........................................................................
64
10.9
QUEUE ENGINE.........................................................................
65
10.9.1 SERVICE ARBITRATION
................................................. 66
10.9.2 CELL QUEUING
............................................................... 67
10.9.3 CLASS SCHEDULING
..................................................... 74
10.9.4 CONGESTION CONTROL
............................................... 76
10.9.5 STATISTICS
..................................................................... 83
10.9.6 MICROPROCESSOR QUEUE BUFFER RE-
ALLOCATION/TEAR DOWN
............................................ 85
10.10 CONTEXT MEMORY SSRAM INTERFACE................................
85
10.11 CELL BUFFER SDRAM INTERFACE
......................................... 90
10.12 JTAG TEST ACCESS PORT
....................................................... 93
11
PERFORMANCE
................................................................................... 94
11.1
THROUGHPUT
........................................................................... 94
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PM7329 S/UNI-APEX-LITE
DATASHEET
PMC-2010141
ATM TRAFFIC MANAGER AND SWITCH
11.2
11.3
12
LATENCY
.................................................................................... 96
CDV.............................................................................................
96
REGISTER.............................................................................................
97
12.1
12.2
12.3
12.4
12.5
GENERAL CONFIGURATION AND STATUS..............................
98
LOOP CELL INTERFACE
......................................................... 107
WAN CELL INTERFACE
............................................................113
MEMORY PORT
........................................................................119
SAR...........................................................................................
125
12.5.1 RECEIVE........................................................................
125
12.5.2 TRANSMIT
..................................................................... 127
12.5.3 CELL BUFFER DIAGNOSTIC ACCESS.........................
128
12.6
12.7
12.8
QUEUE ENGINE.......................................................................
129
MEMORY INTERFACE
............................................................. 144
CBI INTERFACE
....................................................................... 145
13
14
CBI REGISTER PORT MAPPING
....................................................... 147
MEMORY PORT MAPPING.................................................................
153
14.1
14.2
CONTEXT SIZE AND LOCATION.............................................
153
QUEUE CONTEXT DEFINITION
.............................................. 156
14.2.1 VC CONTEXT RECORDS..............................................
157
14.2.2 PORT CONTEXT RECORDS.........................................
165
14.2.3 CLASS CONTEXT RECORDS
....................................... 169
14.2.4 SHAPING CONTEXT RECORDS...................................
174
14.2.5 CELL CONTEXT RECORD
............................................ 176
14.2.6 MISC CONTEXT
............................................................ 176
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii