PDSP16256A/C0/AC datasheet, PDF

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PDSP16256A/C0/AC: DescriptionMultiplier Accumulator/Summer, 16-Bit, CMOS, CPGA144, PGA-144; CategoryThe embedded processor and controller Microcontrollers and processors; File Size172KB，25 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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PDSP16256A/C0/AC Overview

Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA144, PGA-144

PDSP16256A/C0/AC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zarlink Semiconductor (Microsemi)
package instruction	PGA, PGA144,15X15
Reach Compliance Code	compliant
boundary scan	NO
maximum clock frequency	25 MHz
External data bus width	16
JESD-30 code	S-CPGA-P144
JESD-609 code	e0
length	40.005 mm
low power mode	NO
Number of terminals	144
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	16
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA144,15X15
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	6.15 mm
Maximum slew rate	320 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
width	40.005 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER

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PDSP16256/A

Programmable FIR Filter

DS3709

ISSUE 7.1

June 1999

Features

Ordering Information

Commercial (0

C to

170

PDSP16256A/C0/AC 25MHz, PGA package

Industrial (240

C to

185

PDSP16256 B0/AC 20MHz, PGA package

PDSP16256 B0/GC 20MHz, QFP package

Military (255

C to

1125

PDSP16256 MC/AC1R 20MHz, MIL-STD-883*

(latest revision), PGA package

PDSP16256 MC/GC1R 20MHz, MIL-STD-883*

(latest revision), QFP package

*See notes following Electrical Characteristics for further

information on MIL-STD-883 screening

Sixteen MACs in a Single Device

Basic Mode is 16-Tap Filter at up to 25MHz

Sample Rates

Programmable to give up to 128 Taps with

Sampling Rates Proportionally Reducing to

3·125MHz

16-bit Data and 32-bit Accumulators

Can be configured as One Long Filter or Two

Half-Length Filters

Decimate-by-two Option will Double the Filter

Length

Coefficients supplied from Host System or local

EPROM

Applications

Associated Products

PDSP16350

I/Q Splitter/NCO

PDSP16510A

FFT Processor

High Performance Digital Filters

Description

The PDSP16256 contains sixteen multiplier -

accumulators, which can be multi cycled to provide

from 16 to 128 stages of digital filtering. Input data

and coefficients are both represented by 16-bit

two’s complement numbers with coefficients

converted internally to 12 bits and the results being

accumulated up to 32 bits.

In 16-tap mode the device samples data at the

system clock rate of up to 25MHz. If a lower sample

rate is acceptable then the number of stages can be

increased in powers of two up to a maximum of 128.

Each time the number of stages is doubled, the

sample clock rate must be halved with respect to the

system clock. With 128 stages the sample clock is

therefore one eighth of the system clock.

In all speed modes devices can be cascaded to

provide filters of any length, only limited by the

possibility of accumulator overflow. The 32-bit

results are passed between cascaded devices

without any intermediate scaling and subsequent

loss of precision.

The device can be configured as either one long

filter or two separate filters with half the number of

taps in each. Both networks can have independent

inputs and outputs.

Both single and cascaded devices can be operated

in decimate-by-two mode. The output rate is then

half the input rate, but twice the number of stages

are possible at a given sample rate. A single device

with a 20MHz clock would then, for example,

provide a 128-stage low pass filter, with a 5MHz

input rate and 2·5MHz output rate.

Coefficients are stored internally and can be down

loaded from a host system or an EPROM. The latter

requires no additional support, and is used in stand

alone applications. A full set of coefficients is then

automatically loaded at power on, or at the request

of the system. A single EPROM can be used to

provide coefficients for up to 16 devices.

PDSP16256/A

Signal

DA15:0

DB15:0

X31:0

16-bit data input bus to Network A.

Delayed data output bus in the single filter mode. Connected to the data input bus of the next device in a

cascaded chain. Input to Network B in the dual filter modes.

Expansion input bus in the single filter mode. Connected to the previous filter output in a cascaded chain.

The inputs are not used on a single device system or on the Termination device in a cascaded chain. The

X bus provides the output from Network B in both dual modes.

In single filter mode this bus holds the main device output. In dual mode it holds the output from Network A.

Filter enable. The first high present on an SCLK rising edge defines the first data sample. The control register

and coefficient memory must be configured befor FEN is enabled.The signal must stay active whilst valid

data is being received and must be low if FRUN is high.

Delayed filter enable. This output is connected to the Filter Enable input of the next device in a cascaded

chain when moving towards the termination device and with multiple stand-alone EPROM-loaded

configurations. It is used to coordinate the control logic within each device.

Selects either the upper or lower set of coefficients for Bank Swap. A low selects the lower bank, a high the

upper bank.

In EPROM load mode, when high this signal allows continuous filter operations to occur without the need for

the initial FEN edge. If the device is not a single, interface or master device then this pin must be tied low.

A low on this signal on the SCLK rising edge will clear all the internal accumulators.

DCLR

need only remain

low for a single cycle, signal BUSY will indicate when the internal clearing is complete. After a clear the

device must be re-synchronised to the data stream using FEN. It is recommended that FEN is taken low

at the same time as clear. FEN may then be taken high to synchronise the data stream once BUSY has

returned low.

C15:0

A7:0

CCS

WEN

BYTE

EPROM

Description

F31:0

FEN

DFEN

SWAP

FRUN

DCLR

16-bit coefficient input bus. In the Byte mode of operation, C15:8 have alternative uses as explained in the

text.

Coefficient address bus. In the EPROM mode A7:0 are address outputs for an EPROM. In the remote host

mode they are inputs from the host. A7 is not used when coefficients are loaded as 16-bit words.

This pin is similar in operation to A7:0 and provides a higher order address bit. When low the coefficients

are loaded, when high the control register is loaded.

In the remote mode this pin is an input which when low enables the load operation. In the EPROM mode

it is an output which provides the write enable for other slave devices.

This pin is always an input and must also be low for the internal write operation to occur.

When this pin is tied low, coefficients are loaded as two 8-bit bytes. When the pin is high they are loaded

as 16-bit words. In the EPROM mode this pin is ignored.

When this pin is tied low coefficients are loaded as bytes from an external EPROM. The device outputs an

address on A7:0. When the pin is high coefficients must be loaded from a remote master. They can then

be transferred individually rather than as a complete set.

The main system clock; all operations are synchronous with this clock. The clock rate must be either 1, 2,

4, or 8 times the required data sampling rate. The factor used depends on the required filter length.

This output, when used to enable SCLK, can provide a data sampling clock. It has the effect of dividing the

SCLK rate by 1, 2, 4 or 8 depending on the filter mode selected.

Tri-state enable for the F bus. When high the outputs will be high impedance.

OEN

is registered onto the

device and does not therefore take effect until the first SCLK rising edge

SCLK

CLKOP

OEN

BUSY

RES

A high on this signal indicates that the device is completing internal operations and is not yet able to accept

new data. The signal is used during automatic EPROM loading, reset and accumulator clearing.

When this pin is low the control logic and accumulators are reset. In the EPROM mode it will initiate a load

sequence when it goes high.

NOTES

1. Unused buses (e.g. X31:0 when the device is configured in single or termination mode) can be set to any value. They should however be

maintained at a valid logic level to avoid an increase in power consumption.

2. To ensure correct input voltage thresholds are maintained all the V

and GND pins must be connected to adequate power and ground planes.

Table 1 Pin descriptions

PDSP16256A/C0/AC Related Products

	PDSP16256A/C0/AC	PDSP16256B0/GC	PDSP16256B0/AC	PDSP16256MC/GC1R
Description	Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA144, PGA-144	Multiplier Accumulator/Summer, 16-Bit, CMOS, CQFP172, QFP-172	Multiplier Accumulator/Summer, 16-Bit, CMOS, CPGA144, PGA-144	Multiplier Accumulator/Summer, 16-Bit, CMOS, CQFP172, QFP-172
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	PGA, PGA144,15X15	QFF, QFL172,1.2SQ,25	PGA, PGA144,15X15	QFF, QFL172,1.2SQ,25
Reach Compliance Code	compliant	compliant	compliant	compliant
boundary scan	NO	NO	NO	NO
maximum clock frequency	25 MHz	20 MHz	20 MHz	20 MHz
External data bus width	16	16	16	16
JESD-30 code	S-CPGA-P144	S-CQFP-F172	S-CPGA-P144	S-CQFP-F172
JESD-609 code	e0	e0	e0	e0
length	40.005 mm	29.21 mm	40.005 mm	29.21 mm
low power mode	NO	NO	NO	NO
Number of terminals	144	172	144	172
Maximum operating temperature	70 °C	85 °C	85 °C	125 °C
Minimum operating temperature	-	-40 °C	-40 °C	-55 °C
Output data bus width	16	16	16	16
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	QFF	PGA	QFF
Encapsulate equivalent code	PGA144,15X15	QFL172,1.2SQ,25	PGA144,15X15	QFL172,1.2SQ,25
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	FLATPACK	GRID ARRAY	FLATPACK
Peak Reflow Temperature (Celsius)	225	225	225	225
power supply	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	6.15 mm	3.58 mm	6.15 mm	3.58 mm
Maximum slew rate	320 mA	250 mA	250 mA	380 mA
Maximum supply voltage	5.25 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.75 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	NO	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	FLAT	PIN/PEG	FLAT
Terminal pitch	2.54 mm	0.635 mm	2.54 mm	0.635 mm
Terminal location	PERPENDICULAR	QUAD	PERPENDICULAR	QUAD
Maximum time at peak reflow temperature	30	30	30	30
width	40.005 mm	29.21 mm	40.005 mm	29.21 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER

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