D Latch, 4000/14000/40000 Series, 1-Func, Low Level Triggered, 1-Bit, True Output, CMOS, CDIP16, METAL SEALED, CERAMIC, DIP-16
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Harris |
| package instruction | DIP, DIP16,.3 |
| Reach Compliance Code | unknown |
| Other features | 1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH |
| series | 4000/14000/40000 |
| JESD-30 code | R-CDIP-T16 |
| JESD-609 code | e0 |
| Load capacitance (CL) | 50 pF |
| Logic integrated circuit type | D LATCH |
| MaximumI(ol) | 0.00036 A |
| Number of digits | 1 |
| Number of functions | 1 |
| Number of terminals | 16 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| Output polarity | TRUE |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP16,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5/15 V |
| Prop。Delay @ Nom-Sup | 400 ns |
| Certification status | Not Qualified |
| Filter level | 38535Q/M;38534H;883B |
| Maximum seat height | 5.08 mm |
| Maximum supply voltage (Vsup) | 18 V |
| Minimum supply voltage (Vsup) | 3 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| Trigger type | LOW LEVEL |
| width | 7.62 mm |
FPGA/CPLD
Embedded System
RF/Wirelessly
Domestic Chip Exchange
51mcu
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