CT43DJ-FREQ-OUT23 datasheet, PDF

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CT43DJ-FREQ-OUT23: DescriptionCMOS/TTL Output Clock Oscillator, 0.01MHz Min, 69.999MHz Max,; CategoryPassive components oscillator; File Size104KB，1 Pages; ManufacturerCal Crystal Lab Inc / Comclok Inc; Websitehttps://www.transko.com

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CT43DJ-FREQ-OUT23 Overview

CMOS/TTL Output Clock Oscillator, 0.01MHz Min, 69.999MHz Max,

CT43DJ-FREQ-OUT23 Parametric

Parameter Name	Attribute value
Maker	Cal Crystal Lab Inc / Comclok Inc
Reach Compliance Code	compliant
maximum descent time	6 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
Installation features	SURFACE MOUNT
Maximum operating frequency	69.999 MHz
Minimum operating frequency	0.01 MHz
Maximum operating temperature	50 °C
Minimum operating temperature	-10 °C
Oscillator type	CMOS/TTL
Output load	10 TTL, 20 pF
physical size	13.21mm x 13.21mm x 6.1mm
longest rise time	6 ns
Nominal supply voltage	5 V
surface mount	YES
maximum symmetry	47.5/52.5 %

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Cal Crystal Lab, Inc. / Comclok, Inc. 800-333-9825

1156 North Gilbert Street • Anaheim, CA 92801

TRI-STATE ENABLE/DISABLE OSCILLATORS / HCMOS / TTL

(FULL & HALF SIZE)

MODEL CT

5.0VDC

Model

Frequency Range

Frequency Stability

Operating Temperature Range

Storage Temperature Range

Current Consumption

Supply Voltage

Symmetry

Rise & Fall Time (Tr & Tf)

Logic “1”

Logic “0”

Output Load (Max)

Aging

Enable Input

10kHz ~ 69.999MHz

100ppm Standard, Optional Tolerances Available

C ~+70

C Extended Temperature Ranges Available

-55

C ~+125

10.0KHz ~ 23.999MHz:

15mA Max

24.000MHz ~ 69.999MHz: 30mA Max

+5 VDC

10%

60/40 @ 50% Vcc, Optional Tolerances Available

6 nSec Max

4.5 VDC Min

0.5 VDC Max

10TTL / 20pF

< 5ppm per year

Enable - Logic “1” 2.0 VDC Min

Disable - Logic “0” 0.5 VDC Max

70MHz ~ 160.0MHz

100ppm Standard, Optional Tolerances Available

C ~+70

C Extended Temperature Ranges Available

-55

C ~+125

70.0MHz ~ 99.9MHz:

30mA Max

100.00MHz ~ 129.9MHz: 35mA Max

130.00MHz ~ 160.00MHz: 40mA Max

+5 VDC

10%

60/40 @ 50% Vcc, Optional Tolerances Available

3 nSec Max

4.5 VDC Min

0.5 VDC Max

2TTL / 15pF

< 5ppm per year

Enable - Logic “1” 2.0 VDC Min

Disable - Logic “0” 0.5 VDC Max

FULL SIZE TRI-STATE

PINS

CONNECTIONS

ENABLE / DISABLE

GND

OUTPUT

+5 VDC

±10%

TEST CIRCUIT FULL SIZE

HALF SIZE TRI-STATE

PINS

CONNECTIONS

ENABLE / DISABLE

GND

OUTPUT

+5 VDC

±10%

TEST CIRCUIT HALF SIZE

NOTE:

Capacitance includes probe and test jig 20pF typical (10kHz ~ 69.999MHz)

Capacitance includes probe and test jig 15pF typical (70MHz ~ 160.000MHz)

2. R

= 400Ω - 10TTL

2kΩ - 10LSTTL

3. All diodes are 1N941, 1N43064 or equivalent

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