KM4132G271B
CMOS SGRAM
8Mbit SGRAM
128K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 2.4
May 1998
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 2.4 (May 1998)
KM4132G271B
Revision History
Revision 2.4 (May 1998)
• Added KM4132G271B-7 product(143MHz @ CL =3).
CMOS SGRAM
Revision 2.3 (March 1998)
• Added Reverse Type Package in
ODERING INFORMATION and PIN CONFIGURATION.
• Removed KM4132G271B-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3).
• Changed the Current values of ICC1, ICC3N, ICC4, ICC5, ICC6, ICC7 in
DC CHARACTERISTICS.
• Changed tSAC from 6 to 6.5 @ 125MHz, tSS from 2 to 2.5 @ 125MHz in
AC PARAMETER
.
• Delete a page including
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
Revision 2.1 (November 1997)
•
Changed the Height of TQFP Package from 1.4mmMAX to 1.2mmMax in
PACKAGE DIMENSIONS.
Revision 2.0 (October 1997)
•
Added -H binning(100MHz @ CL =2 ).
•
Changed some values in
DC CHARACTERISTICS.
•
Changed some values in
AC PARAMETER
(tSAC / tOH / tSHZ / tRP / tRC / tBPL / tBWC etc.).
AC PARAMETER
.
•
Changed some values in
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
•
Added the Package Type description(PQFP, TQFP) in
PACKAGE DIMENSIONS.
•
Removed a AC Parameter, tBAL(Block write data-in to Active command period) in
-2-
Rev. 2.4 (May 1998)
KM4132G271B
128K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual bank / Pulse RAS
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
16ms refresh period (1K cycle)
100 Pin PQFP, TQFP (14 x 20 mm)
Reverse Type Package offers the best signal routing
CMOS SGRAM
GENERAL DESCRIPTION
The KM4132G271B is 8,388,608 bits synchronous high data
rate Dynamic RAM organized as 2 x 131,072 words by 32 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.
•
•
•
•
•
•
•
ORDERING INFORMATION
Part NO.
KM4132G271BQ(R)-7
KM4132G271BQ(R)-8
KM4132G271BQ(R)-10
KM4132G271BTQ(R)-7
KM4132G271BTQ(R)-8
KM4132G271BTQ(R)-10
Max Freq.
143MHz
125MHz
100MHz
143MHz
125MHz
100MHz
LVTTL
100 TQFP
LVTTL
100 PQFP
Interface
Package
Graphics Features
• SMRS cycle.
-. Load mask register
-. Load color register
• Write Per Bit(Old Mask)
• Block Write(8 Columns)
* ~G271BQR# / ~G271BTQR# : Reverse Type Package
FUNCTIONAL BLOCK DIAGRAM
DQMi
BLOCK
WRITE
CONTROL
LOGIC
CLK
CKE
CS
MASK
WRITE
MASK
REGISTER
COLOR
REGISTER
INPUT BUFFER
CONTROL
LOGIC
MUX
•
COLUMN
MASK
DQMi
DQi
(i=0~31)
TIMING REGISTER
RAS
CAS
WE
DSF
DQMi
•
128Kx32
CELL
ARRAY
128Kx32
CELL
ARRAY
ROW DECORDER
BANK SELECTION
•
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK ADDRESS(A
0
~A
9
)
-3-
OUTPUT BUFFER
LATENCY &
BURST LENGTH
PROGRAMING
REGISTER
COLUMN
DECORDER
SENSE
AMPLIFIER
Rev. 2.4 (May 1998)
Forward Type
Reverse Type
KM4132G271B
PIN CONFIGURATION
(TOP VIEW)
DQ2
V
SSQ
DQ1
DQ0
V
DD
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
SS
DQ31
DQ30
V
SSQ
DQ29
DQ29
V
SSQ
DQ30
DQ31
V
SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
DQ0
DQ1
V
SSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100 Pin QFP
Reverse Type
20 x 14
§±
0.65
§®
pin Pitch
100 Pin QFP
Forward Type
20 x 14
§±
0.65
§®
pin Pitch
-4-
DQ28
VDDQ
DQ27
DQ26
V
SSQ
DQ25
DQ24
V
DDQ
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
V
SS
V
DD
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A
8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
DQ16
DQ17
V
SSQ
DQ18
DQ19
V
DDQ
V
DD
V
SS
DQ20
DQ21
V
SSQ
DQ22
DQ23
V
DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A
9
)
N.C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
DQ16
DQ17
V
SSQ
DQ18
DQ19
V
DDQ
V
DD
V
SS
DQ20
DQ21
V
SSQ
DQ22
DQ23
V
DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A
9
)
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ28
VDDQ
DQ27
DQ26
V
SSQ
DQ25
DQ24
V
DDQ
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
V
SS
V
DD
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A
8
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A
7
A
6
A
5
A
4
V
SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
A
3
A
2
A
1
A
0
A
0
A
1
A
2
A
3
V
DD
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
SS
A
4
A
5
A
6
A
7
Rev. 2.4 (May 1998)
CMOS SGRAM
KM4132G271B
PIN CONFIGURATION DESCRIPTION
PIN
CLK
CS
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all inputs.
CMOS SGRAM
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock +t
SS
prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
8
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power Supply : +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CKE
Clock
Enable
A
0
~ A
8
A
9
(BA)
RAS
CAS
WE
DQMi
DQi
DSF
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply /Ground
Data Output Power /Ground
No Connection
-5-
Rev. 2.4 (May 1998)
京公网安备 11010802033920号
EEWORLD
