ST72361AR4TA/XXXXE datasheet, PDF - EEWORLD Datasheet

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ST72361AR4TA/XXXXE: Description8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，279 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ST72361AR4TA/XXXXE Overview

8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

ST72361AR4TA/XXXXE Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	64
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G64
length	10 mm
Number of I/O lines	50
Number of terminals	64
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
RAM (bytes)	1536
rom(word)	16384
ROM programmability	MROM
Maximum seat height	1.6 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST72361xx-Auto

8-bit MCU for automotive with Flash or ROM,

10-bit ADC, 5 timers, SPI, LINSCI™

Features

■

Memories

– 16 K to 60 K High Density Flash (HDFlash)

or ROM with read-out protection capability.

In-application programming and in-circuit

programming for HDFlash devices

– 1.5 to 2 K RAM

– HDFlash endurance: 100 cycles, data

retention 20 years at 55 °C

Clock, reset and supply management

– Low power crystal/ceramic resonator

oscillators and bypass for external clock

– PLL for 2 x frequency multiplication

– 5 power saving modes: halt, auto wake up

from halt, active halt, wait and slow

Interrupt management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– TLI top level interrupt (on 64-pin devices)

– Up to 21 external interrupt lines (on 4

vectors)

Up to 48 I/O ports

– Up to 48 multifunctional bidirectional I/O

lines

– Up to 36 alternate function lines

– Up to 6 high sink outputs

5 timers

– 16-bit timer with 2 input captures, 2 output

compares, external clock input, PWM and

pulse generator modes

– 8-bit timer with 1 or 2 input captures, 1 or 2

output compares, PWM and pulse

generator modes

– 8-bit PWM auto-reload timer with 1 or 2

input captures, 2 or 4 independent PWM

output channels, output compare and time

base interrupt, external clock with event

detector

LQFP32 7x7mm

LQFP44 10x10mm

LQFP64 10x10mm

■

– Main clock controller with real-time base

and clock output

– Window watchdog timer

■

■

Up to 3 communications interfaces

– SPI synchronous serial interface

– Master/ slave LINSCI™ asynchronous

serial interface

– Master only LINSCI™ asynchronous serial

interface

Analog peripheral (low current coupling)

– 10-bit A/D converter with up to 16 inputs

– Up to 9 robust ports (low current coupling)

Instruction set

– 8-bit data manipulation

– 63 basic instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

Development tools

– Full hardware/ software development

package

Device summary

Part number

■

■

■

■

■

Table 1.

Reference

ST72361K4-Auto, ST72361K6-Auto,

ST72361K7-Auto, ST72361K9-Auto,

ST72361xx ST72361J4-Auto, ST72361J6-Auto,

-Auto

ST72361J7-Auto, ST72361J9-Auto,

ST72361AR4-Auto, ST72361AR6-Auto,

ST72361AR7-Auto, ST72361AR9-Auto

August 2010

Doc ID 12468 Rev 3

1/279

www.st.com

1

Contents

ST72361xx-Auto

Contents

1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2

3

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3.1

Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1

5.2

5.3

5.4

5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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5.5.2

5.5.3

5.5.4

5.5.5

Contents

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 42

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.6.1

5.6.2

5.6.3

5.6.4

5.6.5

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1

6.2

6.3

6.4

6.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.5.1

6.5.2

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 53

6.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.6.1

6.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1

7.2

7.3

7.4

7.5

7.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.6.1

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.1

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.2.1

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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Contents

8.2.2

8.2.3

ST72361xx-Auto

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.3

8.4

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

I/O port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.4.1

8.4.2

8.4.3

Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Interrupt ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Pull-up input port

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.5

8.6

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9

Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Using halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 85

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.10.1

9.10.2

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Window Register (WDGWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10

Main clock controller with real time clock MCC/RTC . . . . . . . . . . . . . . 87

10.1

10.2

10.3

10.4

10.5

10.6

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Real time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.6.1

MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11

PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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Contents

11.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.2.7

11.2.8

11.2.9

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Counter and prescaler Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Output compare and Time base interrupt . . . . . . . . . . . . . . . . . . . . . . . 94

External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 94

Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

11.3

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

12.1

12.2

12.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

12.3.8

12.3.9

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.4

12.5

12.6

12.7

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.7.1

12.7.2

12.7.3

12.7.4

12.7.5

12.7.6

12.7.7

Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 119

Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 120

Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 120

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Overload protection circuit for 25 ohm speakers

Verilog assign statement usage 1: （1）module assign_test ( clk, lhold, lholda );input clk; input lhold; output lholda;regular maintenance; always @(posedge clk) if (lhold) lholda=lhold; else lholda=0;endmodule...; eeleader-mcu FPGA/CPLD

After installing NXP FRDM-KW41Z and USB-KW41Z, the computer occasionally displays a blue screen: I am using a Lenovo T460P laptop computer, and the operating system is WIN10 Home Chinese Edition. It used to work very stably and never had any system errors. But after installing the software relate...; bjemt NXP MCU

Mouser first experience + CC2650STK SensorTag hands-on experience and comparison with 1: I bought a SensorTag1 on the forum before, and when I saw TI released the SensorTag2, I wanted to buy one to try, but I gave up because of the troublesome registration on the TI website and the intern...; szqt Wireless Connectivity

SJF 2440 Friends who just needed it, come and get it.: SJF 2440 Friends who need it just now, please come and get it....; liusuper_0 MCU

Why does EVC4.0 change the standard SDK to pocket pc 2003 CPU to 100%: Because of this problem: hello.rc(13) : fatal error RC1015: cannot open include file 'aygshell.h', I need to change the second item on the third line of the toolbar from standard sdk to pocket pc 2003...; hulala Embedded System

【Reprint】Discussion on the method of measuring GPS device sensitivity in OTA darkroom (Part 1): Sensitivity is one of the most important tests to measure the capabilities of a GPS receiver. In fact, many consumer-grade GPS receivers usually only perform RF testing during the final receiver produ...; lyzhangxiang RF/Wirelessly

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