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NC7SZ373 TinyLogic UHS D-Type Latch with 3-STATE Output
June 1998
Revised August 2004
NC7SZ373
TinyLogic
UHS D-Type Latch with 3-STATE Output
General Description
The NC7SZ373 is a single positive edge-triggered D-type
CMOS Latch with 3-STATE output from Fairchild’s Ultra
High Speed Series of TinyLogic
in the space saving
SC70 6-lead package. The device is fabricated with
advanced CMOS technology to achieve ultra high speed
with high output drive while maintaining low static power
dissipation over a very broad V
CC
operating range. The
device is specified to operate over the 1.65V to 5.5V range.
The inputs and output are high impedance when V
CC
is 0V.
Inputs tolerate voltages up to 7V independent of V
CC
oper-
ating voltage. The latch appears transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is latched. The output toler-
ates voltages above V
CC
in the 3-STATE condition.
Features
s
Space saving SC70 6-lead package
s
Ultra small MicroPak
leadless package
s
Ultra High Speed; t
PD
2.6 ns Typ into 50 pF at 5V V
CC
s
High Output Drive;
±
24 mA at 3V V
CC
s
Broad V
CC
Operating Range; 1.65V to 5.5V
s
Matches the performance of LCX when operated at
3.3V V
CC
s
Power down high impedance inputs/output
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Order
Number
NC7SZ373P6X
NC7SZ373L6X
Package
Number
MAA06A
MAC06A
Product Code
Top Mark
Z73
D4
Package Description
6-Lead SC70, EIAJ SC88, 1.25mm Wide
6-Lead MicroPak, 1.0mm Wide
Supplied As
3k Units on Tape and Reel
5k Units on Tape and Reel
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2004 Fairchild Semiconductor Corporation
DS500157
www.fairchildsemi.com
NC7SZ373
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignments for SC70
Pin Descriptions
Pin Names
D
LE
OE
Q
Description
Data Input
Latch Enable Input
Output Enable Input
Latch Output
Pin One Orientation Diagram
(Top View)
Function Table
Inputs
LE
H
H
L
X
D
L
H
X
X
OE
L
L
L
H
Output
Q
L
H
Q
n-1
Z
Pad Assignments for MicroPak
AAA
=
Product Code Top Mark - see ordering code
Note:
Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin.(see diagram).
H
=
HIGH Logic Level
X
=
Immaterial
L
=
LOW Logic Level
Z
=
HIGH Impedance
Q
n-1
=
Previous state prior to HIGH-to-LOW transition of latch enable
(Top Thru View)
www.fairchildsemi.com
2
NC7SZ373
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
DC Input Diode Current (I
IK
)
V
IN
<
0V
DC Output Diode Current (I
OK
)
V
OUT
<
0V
DC Output (I
OUT
) Source/Sink Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
Junction Temperature under Bias (T
J
)
Junction Lead Temperature (T
L
)
(Soldering, 10 seconds)
Power Dissipation (P
D
) @
+
85
°
C
260
°
C
180 mW
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50 mA
−
50 mA
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
150
°
C
Recommended Operating
Conditions
(Note 2)
Power Supply
Operating (V
CC
)
Data Retention
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Active State
3-STATE
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
1.8V, 2.5V
±
0.2V
V
CC
=
3.3V
±
0.3V
V
CC
=
5.5V
±
0.5V
Operating Temperature (T
A
)
Thermal Resistance (
θ
JA
)
0 to 20 ns/V
0 to 10 ns/V
0 to 5 ns/V
0V to V
CC
0V to 5.5V
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
−
40
°
C to
+
85
°
C
350
°
C/W
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Control
Input Voltage
LOW Level Control
Input Voltage
HIGH Level Control
Output Voltage
V
CC
(V)
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
1.65
1.8
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
V
OL
LOW Level Control
Output Voltage
1.65
1.8
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
I
IN
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE
Output Leakage
Power-Off Leakage Current
Quiescent Supply Current
0 to 5.5
1.65 to 5.5
0.0
1.65 to 5.5
1.55
1.7
2.2
2.9
4.4
1.24
1.9
2.4
2.3
3.8
1.65
1.8
2.3
3.0
4.5
1.52
2.15
2.8
2.68
4.2
0.0
0.0
0.0
0.0
0.0
0.08
0.10
0.15
0.22
0.22
0.08
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
±0.1
±0.5
1.0
1.0
Min
0.7 V
CC
0.25 V
CC
0.3 V
CC
1.55
1.7
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
0.0
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
±1.0
±5.0
10
10
µA
µA
µA
µA
V
V
IN
=
V
IL
I
OL
=
4 mA
I
OL
=
8 mA
I
OL
=
16 mA
I
OL
=
24 mA
I
OL
=
32 mA
0
≤
V
IN
≤
5.5V
V
IN
=
V
IL
or V
IH
0
≤
V
OUT
≤
5.5V
V
IN
or V
OUT
=
5.5V
V
IN
=
5.5V, GND
I
OL
=
100
µA
V
V
IN
=
V
IH
I
OH
= −4
mA
I
OH
= −8
mA
I
OH
= −16
mA
I
OH
= −24
mA
I
OH
= −32
mA
I
OH
= −100 µA
1.65 to 1.95 0.75 V
CC
T
A
= +25°C
Typ
Max
T
A
= −40°C
to
+85°C
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
Max
Unit
V
V
Conditions
3
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NC7SZ373
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
D to Q
V
CC
(V)
1.65
1.8
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
LE to Q
1.65
1.8
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
PZL
t
PZH
Output Enable Time
1.65
1.8
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
t
PLZ
t
PHZ
Output Disable Time
1.65
1.8
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
t
S
Setup Time,
D to LE
t
H
Hold Time,
D to LE
t
W
Pulse Width, LE
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
Min
2.0
2.0
1.5
1.0
1.0
1.5
1.0
2.0
2.0
1.8
1.3
1.0
1.5
1.3
2.0
2.0
2.0
1.5
1.0
2.0
2.0
2.0
1.5
1.0
T
A
= +25°C
Typ
9.0
6.1
3.6
2.7
2.0
3.3
2.6
9.0
6.0
3.5
2.6
2.0
3.3
2.6
9.0
6.0
3.7
2.8
2.2
7.7
5.1
3.5
2.8
2.3
Max
15.0
10.0
6.5
4.6
3.4
5.5
4.3
1.45
9.6
6.1
4.4
3.2
5.3
4.2
13.5
9.0
6.0
5.0
3.7
12.0
8.0
6.0
4.5
3.7
T
A
= −40°C
to
+85°C
Min
2.0
2.0
1.6
1.2
1.0
1.5
1.3
2.0
2.0
1.5
1.0
0.8
1.5
1.2
2.0
2.0
1.8
1.4
1.0
2.0
2.0
1.8
1.4
1.0
2.0
1.5
1.5
1.5
1.5
1.5
3.0
3.0
3.0
ns
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 5
ns
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 5
ns
Max
16.0
10.5
6.8
5.0
3.7
6.2
4.8
15.0
10.0
6.6
4.8
3.5
6.2
4.6
14.6
9.5
6.6
5.3
3.9
13.0
8.5
6.3
4.7
3.9
ns
C
L
=
50 pF, V
I
=
2x V
CC
R
U
, R
D
=
500Ω
S
1
=
GND for t
PHZ
S
1
=
V
I
for t
PLZ
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 5
Figures
1, 4
ns
C
L
=
50 pF, V
I
=
2x V
CC
R
U
, R
D
=
500Ω
S1
=
GND for t
PZH
S1
=
V
I
for t
PZL
Figures
1, 4
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500Ω, S
1
=
Open
Figures
1, 4
Figures
1, 3
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500Ω, S
1
=
Open
Figures
1, 3
Figures
1, 3
Units
Conditions
Figure
Number
Capacitance
(Note 3)
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(Note 4)
Note 3:
T
A
= +25C,
f
=
1 MHz.
Note 4:
C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
=
(C
PD
)(V
CC
)(f
IN
)
+
(I
CC
static).
Typ
3
4
14
17
Max
Units
pF
pF
pF
Conditions
V
CC
=
Open, V
IN
=
0V or V
CC
V
CC
=
3.3V, V
IN
=
0V or V
CC
V
CC
=
3.3V
V
CC
=
5.0V
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4
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