NC7SZ02
TinyLogic UHS Two-Input
NOR Gate
Description
The NC7SZ02 is a single two−input NOR gate from
ON Semiconductor’s Ultra−High Speed (UHS) series of TinyLogic.
The device is fabricated with advanced CMOS technology to achieve
ultra−high speed with high output drive while maintaining low static
power dissipation over a broad V
CC
operating range. The device is
specified to operate over the 1.65 V to 5.5 V V
CC
operating range. The
inputs and output are high−impedance when V
CC
is 0 V. Inputs
tolerate voltages up to 5.5 V, independent of V
CC
operating range.
Features
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MARKING
DIAGRAMS
SIP6 1.45x1.0
CASE 127EB
Pin 1
UDFN6
1.0X1.0, 0.35P
CASE 517DP
Pin 1
JJKK
XYZ
•
•
•
•
•
•
•
•
•
•
Ultra−High Speed: t
PD
2.4 ns (Typical) into 50 pF at 5 V V
CC
High Output Drive:
±24
mA at 3 V V
CC
Broad V
CC
Operating Range: 1.65 V to 5.5 V
Matches Performance of LCX Operated at 3.3 V V
CC
Power Down High−Impedance Inputs / Outputs
Over−Voltage Tolerance Inputs Facilitate 5 V to 3 V Translation
Proprietary Noise / EMI Reduction Circuitry
Ultra−Small MicroPak™ Packages
Space−Saving SC−74A and SC−88A Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
IEEE / IEC
A
B
≥1
Y
JJ, 7Z02, Z02
KK
XY
Z
M
T
JJKK
XYZ
SC−74A
CASE 318BQ
7Z02T
SC−88A
1.25x2
CASE 419AC−01
Z02T
Figure 1. Logic Symbol
= Specific Device Code
= 2−Digit Lot Run Traceability Code
= 2−Digit Date Code Format
= Assembly Plant Code
= Data Code
= Die Run Code
= Year Coding Scheme
= Plant Code Identifier
= Eight−Week Datacoding Scheme
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 1996
July, 2019
−
Rev. 2
1
Publication Order Number:
NC7SZ02/D
NC7SZ02
Pin Configurations
A 1
B 2
GND 3
5
V
CC
A 1
B 2
6 V
CC
5 NC
4 Y
4
Y
GND 3
Figure 2. SC−88A and SC−74A (Top View)
PIN DEFINITIONS
Pin # SC−88A /
SC74A
1
2
3
4
5
Pin # MicroPak
1
2
3
4
6
5
Name
A
B
GND
Y
V
CC
NC
Description
Input
Input
Ground
Output
Supply Voltage
No Connect
Figure 3. MicroPak (Top Through View)
FUNCTION TABLE
(Y = /A + /B)
Inputs
A
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
B
L
H
L
H
Output
Y
H
L
L
L
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NC7SZ02
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
or I
GND
T
STG
T
J
T
L
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
V
IN
<
−0.5
V
V
IN
> 6.0 V
DC Output Diode Current
V
OUT
<
−0.5
V
V
OUT
> 6 V, V
CC
= GND
DC Output Current
DC V
CC
or Ground Current
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 Seconds)
Power Dissipation in Still Air
SC−74A
SC−88A−5
MicroPak−6
MicroPak2™−6
ESD
Human Body Model, JEDEC: JESD22−A114
Charge Device Model, JEDEC: JESD22−C101
Parameter
Min
−0.5
−0.5
−0.5
−
−
−
−
−
−
−65
−
−
−
−
−
−
−
−
Max
6.0
6.0
6.0
−50
+20
−50
+20
±50
±50
+150
+150
+260
225
190
327
327
4000
2000
V
mA
mA
°C
°C
°C
mW
mA
Unit
V
V
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
Parameter
Supply Voltage Operating
Supply Voltage Data Retention
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Times
V
CC
at 1.8 V, 2.5 V
±0.2
V
V
CC
at 3.3 V
±0.3
V
V
CC
at 5.0 V
±0.5
V
q
JA
Thermal Resistance
SC−74A
SC−88A−5
MicroPak−6
MicroPak2−6
Conditions
Min
1.65
1.5
0
0
−40
0
0
0
−
−
−
−
Max
5.50
5.5
5.5
V
CC
+85
20
10
5
555
659
382
382
°C/W
V
V
°C
ns/V
Unit
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Unused inputs must be held HIGH or LOW. They may not float.
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NC7SZ02
DC ELECTICAL CHARACTERISTICS
T
A
= +25°C
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
V
CC
(V)
1.65 to 1.95
2.30 to 5.50
LOW Level Input Voltage
1.65 to 1.95
2.30 to 5.50
HIGH Level Output Voltage
1.65
1.80
2.30
3.00
4.50
1.65
2.30
3.00
3.00
4.50
V
OL
LOW Level Output Voltage
1.65
1.80
2.30
3.00
4.50
1.65
2.30
3.00
3.00
4.50
I
IN
I
OFF
I
CC
Input Leakage Current
Power Off Leakage Current
Quiescent Supply Current
1.65 to 5.50
0
1.65 to 5.50
I
OL
= 4 mA
I
OL
= 8 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
V
IN
= 5.5 V, GND
V
IN
or V
OUT
= 5.5 V
V
IN
= 5.5 V, GND
I
OH
=
−4
mA
I
OH
=
−8
mA
I
OH
=
−16
mA
I
OH
=
−24
mA
I
OH
=
−32
mA
V
IN
= V
IH
,
I
OL
= 100
mA
V
IN
= V
IL
,
I
OH
=
−100
mA
Conditions
Min
0.65 V
CC
0.70 V
CC
−
−
1.55
1.70
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
−
−
−
−
−
−
−
−
−
−
−
−
−
Typ
−
−
−
−
1.65
1.80
2.30
3.00
4.50
1.52
2.15
2.80
2.68
4.20
0.00
0.00
0.00
0.00
0.00
0.08
0.10
0.15
0.22
0.22
−
−
−
Max
−
−
0.35 V
CC
0.30 V
CC
−
−
−
−
−
−
−
−
−
−
0.10
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
±1
1
2.0
T
A
=
−40
to +85°C
Min
0.65 V
CC
0.70 V
CC
−
−
1.55
1.70
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
−
−
−
−
−
−
−
−
−
−
−
−
−
Max
−
−
0.35 V
CC
0.30 V
CC
−
−
−
−
−
−
−
−
−
−
0.10
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
±10
10
20
mA
mA
mA
V
V
V
Unit
V
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NC7SZ02
AC ELECTRICAL CHARACTERISTICS
T
A
= +25°C
Symbol
t
PLH
, t
PHL
Parameter
Propagation Delay
(Figure 4, 5)
V
CC
(V)
1.65
1.80
2.50
±0.20
3.30
±0.30
5.00
±0.50
3.30
±0.30
5.00
±0.50
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(Note 2) (Figure 6)
0
3.30
5.00
C
L
= 50 pF,
R
L
= 500
W
Conditions
C
L
= 15 pF,
R
L
= 1 MW
Min
−
−
−
−
−
−
−
−
−
−
Typ
5.3
4.4
2.9
2.3
1.9
2.9
2.4
4
23
30
Max
11.5
9.5
6.5
4.5
3.9
5.0
4.3
−
−
−
T
A
=
−40
to +85°C
Min
−
−
−
−
−
−
−
−
−
−
Max
12.0
10.0
7.0
4.7
4.1
5.2
4.5
−
−
−
pF
pF
Unit
ns
2. C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at
no output loading and operating at 50% duty cycle. C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
= (C
PD
) (V
CC
) (f
IN
) + (I
CC
static).
t
r
= 3 ns
90%
INPUT
V
CC
10%
50%
t
W
t
PHL
90%
50%
10%
GND
t
f
= 3 ns
V
CC
INPUT
C
L
R
L
OUTPUT
OUTPUT
t
PLH
V
OH
50%
50%
V
OL
Figure 4. AC Test Circuit
V
CC
A
INPUT
Figure 5. AC Waveforms
NOTE:
3. Input = AC Waveform; t
r
= t
f
= 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%.
Figure 6. I
CC
D Test Circuit
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