SP6652/SP6652A
1A, High Efficiency, Fixed 1.4 MHz
Current Mode PWM Buck Regulator
FEATURES
■
1A Output Current
■
1.4MHz Constant Frequency Operation
■
97% Efficiency Possible
■
0.5µA (Max.) Shutdown Current
■
Adjustable Output Down to 0.8V
■
No External FETs or Schottky Diode Required
■
Uses Small Value Inductors and Ceramic
Output Capacitors
■
Low Dropout Operation: 100% Duty Cycle
■
Soft Start and Thermal Shutdown Protection
■
Easy Frequency Synchronization
■
Small (3mm X 3mm) 10 Pin DFN or MSOP
Package
PGND
S
GND
FB
COMP
SD
1
2
3
4
5
10
LX
PVIN
SVIN
SYNC
MODE
SP6652
10 Pin DFN
9
8
7
6
Now Available in Lead Free Packaging
APPLICATIONS
■
Mobile Phones
■
PDAs
■
DSCs
■
MP3 Players
■
USB Devices
■
Point of Use Power
DESCRIPTION
The SP6652 is a high efficiency, synchronous buck regulator ideal for portable applications
using one Li-Ion cell, with up to 1A of output current. The 1.4MHz switching frequency and
PWM control loop are optimized for a small value inductor and ceramic output capacitor,
for space constrained portable designs. In addition, the input voltage range of 2.7V to 5.5V,
excellent transient response, output accuracy, and ability to transition into 100% duty cycle
operation -- further extending useful battery life -- make the SP6652 a superior choice for
a wide range of portable power applications. A logic level shutdown control, external clock
synchronization, and forced-PWM or automatic control inputs are provided. Other features
include soft-start, overcurrent protection and 140ºC over-temperature shutdown.
TYPICAL APPLICATION CIRCUIT
V
OUT
3.3V at 1A
340kΩ
10µF
100kΩ
4kΩ
10nF
ENABLE
SHUTDOWN
4.7µH
1
2
3
4
5
P
GND
S
GND
FB
COMP
SD
LX
P
VIN
10
9
8
7
6
10Ω
1µF
SP6652
3.6V - 5.5V
V
IN
S
VIN
SYNC
MODE
10µF
Date: 09/07/06 Rev I
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
© 2006 Sipex Corporation
1
PV
IN
,S
VIN
...........................................................................-0.3V to 6.0V
P
GND
to S
GND
....................................................................-0.3V to 0.3V
LX to P
GND
.............................................................. - 0.3V to P
VIN
+0.3V
Storage Temperature ....................................................-65 °C to 150 °C
Operating Temperature.................................................. -40°C to +85°C
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sec-
tions of the specifications below is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect
reliability.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
V
IN
= V
SDN
= 3.6V, I
O
= 0mA, T
AMB
= -40°C to +85°C, typical values at 27°C unless otherwise noted.
The
♦
denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN
2.85
0.784
-1
-4
1.2
(SP6652)
(SP6652A)
200
1.0
-1
0.01
0.3
1.7
0.4
0.4
1.3
-3
1.5
0.1
0.6
0.6
1.7
3
1.4
100
0.8
0.01
TYP MAX UNITS
5.5
0.816
1
4
1.6
200
400
2.0
1
0.6
V
V
CONDITIONS
Input Operating Voltage
FB Set Voltage
FB Set Current
Overall FB Accuracy
Switching Frequency
Minimum On-Time-Duration
SYNC Tracking Frequency
SYNC Input Current
SYNC Logic Threshold Low
SYNC Logic Threshold High
PMOS Switch Resistance
NMOS Switch Resistance
Inductor Current Limit
LX Leakage Current
V
IN
Quiecent Current
♦
♦
♦
♦
Result of I
Q
measurement at V
IN
= P
VIN
= 5.5V
µ
A
%
MHz
ns
MHz
V
FB
= 0.8V
FB = COMP
Mode = SD = V
IN
V
FB
= 1.0V, V
COMP
= 0.2V
♦
♦
♦
♦
♦
♦
♦
♦
Mode = SD = V
IN
, V
FB
=1.0V
µ
A
V
V
Ω
Ω
A
High-to-Low Transition
Low-to-High Transition
I
PMOS
= 200mA
I
NMOS
= 200mA
V
FB
= 0.4V, Mode = SD = V
IN
SD = 0.0V
V
IN
= 3.6V, Mode = SD = V
IN
V
IN
= 5.5V, Mode = SD = V
IN
µ
A
mA
mA
V
%
1
3
2.55
2.7
6
1
-1
0.6
2
0.01
0.9
1.25
700
140
14
1
5
10
2.85
UVLO Undervoltage Lockout Threshold,
V
IN
falling
UVLO hysteresis
Soft Start Current
SD
MODE Input Current
SD
MODE Input Threshold Voltage
♦
SD = V
IN
4
1
µ
A
µ
A
V
V
mA/
µ
S
♦
♦
♦
♦
SD = V
IN
, V
COMP
= 1V
High-to-Low Transition
Low-to-High Transition
1.8
Slope Compensation
Rising Over-Temperature Trip Point
Over-Temperature Hysteresis
Error Amplifier Transconductance
°
C
°
C
mA/V
Date: 09/07/06 Rev I
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
© 2006 Sipex Corporation
2
PIN DESCRIPTION
PIN NUMBER
1
2
3
PIN NAME
P
GND
S
GND
FB
DESCRIPTION
Power Ground Pin. Synchronous rectifier current returns through this
pin.
Internal Ground Pin. Control circuitry returns current to this pin.
External feedback network input connection. Connect a resistor from
FB to ground and from FB to V
OUT
to control the output voltage.
Regulation point at FB = 0.8V Typical.
Compensation pin for error loop. Connect an R and C in series to
ground to control open loop pole and zero.
5
6
7
8
9
10
SD
4
COMP
MODE
SYNC
S
VIN
P
VIN
LX
Shutdown control input. Tie pin to V
IN
for normal operation, tie to
ground for shutdown. TTL input threshold.
Connect this pin to V
IN
.
An external clock signal can be connected to this pin to synchronize
the switching frequency.
Internal supply voltage. Control circuitry is powered from this pin.
Use an RC filter close to the pin to cut down supply noise.
Supply voltage for the output driver stage. Inductor charging current
passes through this pin.
Inductor switching node. Inductor tied between this pin and the output
capacitor to create regulated output voltage.
Date: 09/07/06 Rev I
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
© 2006 Sipex Corporation
3
FUNCTIONAL DIAGRAM
Date: 09/07/06 Rev I
V
IN
SD
S
VIN
+V
P
VIN
Reference
V0P3R
VREF
Shutdown
NOSWITCH
0.3V
0.75V
REFOK
Internal
Supply
7.5mV
PWM Mode Comparator
0.75V
GO PWM
PFM Loop Comparator
RST
Charging
PMOS
Replica
Slope Compensation
CLK
Current Loop Comparator
ILPK
ILPK
LX
7.5mV
Changing
PMOS
0.75V
CHG
+V
Soft Start
2uA
S
R
Qn
Q
SD
L1
VOUT
300mA
M
CHG
R
Driver
REFOK
SOFT
STRT
Translator
GO PWM
R
S
CLR
S
Co
CLR
RF1
Pre-amp
Error Amp
Mode Select
CLK
0.75V
RL
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
A
GO PFM
PWM/PFM
DCHG
4
PFM
PARK
A=3
Gm
+V
RF2
PFM Node Park Clamp
SOFT
STRT
BLIM
Q1
Q2
FB_LO
GO PFM
CNTR
+
-
+
-
Peak and Trough Current Detector
- by 2
100mA
PGND
LX
0mA
DCHG
CLAMP
OSC
SYNC
Low Vo Indicator
0.3V
PWM/PFM
Inductor Current Clamp
CLK
Clock Generator
Internal
GND
SGND
FB_LO
FB
COMP
MODE
SYNC
© 2006 Sipex Corporation
Date: 06/38/06 Rev F
SP6652 1A, High Efficiency, Fixed 1.4MHz Current Mode PWM Buck Regulator
© Copyright 2005 Sipex Corporation
DETAILED DESCRIPTION
Current Mode Control and Slope
Compensation
The SP6652 is designed to use low value
ceramic capacitors and low value inductors
to reduce the converterʼs volume and cost
in portable devices. Current mode PWM
control was, therefore, chosen for the ease
of compensation when using ceramic output
capacitors and better transient line rejec-
tion, which is important in battery powered
applications. Current mode control spreads
the two poles of the output power train filter
far apart so that the modulator gain crosses
over at -20dB/decade instead of the usual
-40dB/decade. The external compensation
network is, simply, a series RC circuit con-
nected between ground and the output of the
internal transconductance error amplifier.
It is well known that an unconditional insta-
bility exists for any fixed frequency current-
mode converter operating above 50% duty
cycle. A simple, constant-slope compensa-
tion is chosen to achieve stability under these
conditions. The most common high duty
cycle application is a Li-Ion battery-powered
regulator with a 3.3V output (D ≥ 90%). Since
the current loop is critically damped when the
compensation slope (denoted MC
V
) equals
the negative discharge slope (denoted M2
V
),
the amount of slope compensation chosen
is, therefore:
M2 = dI
L
/dT
OFF
= -V
OUT
/L = -3.3V/4.7µH =
-702mA/µs
M2
V
= M2*R
PMOS
MC
V
= -M2
V
= 702mA/µs*0.2Ω = 140mV/µs,
for R
PMOS
= 0.20Ω
The inductor current is sensed as a voltage
across the PMOS charging switch and the
NMOS synchronous rectifier (see BLOCK
DIAGRAM). During inductor current charge,
V(PV
IN
)-V(LX) represents the charging cur-
Date: 09/07/06 Rev I
rent ramp times the resistance of the PMOS
charging switch. To keep the effective current
slope compensation constant (remembering
current is being compensated, not voltage)
the voltage slope must be proportional to
R
PMOS
. To account for this, the slope com-
pensation voltage is internally generated
with a bias current that is also proportional
to R
PMOS
.
Over Current Protection
In steady state closed loop operation the
voltage at the COMP pin controls the duty
cycle. Due to the current mode control and the
slope compensation, this voltage will be:
V(
COMP
) = {I
LPK
* R
PMOS
+ MC
V
* T
ON
+
V
BE
(Q1)}
The COMP node will be clamped when its
voltage tries to exceed V(
BLIM
) + V
BE
(Q1).
The V
BE
(Q1) term is cancelled by V
BE
(Q2)
at the output of the translator. The correct
value of clamp voltage is, therefore:
V(
BLIM
) =
I
L
(
MAX
)* R
PMOS
+ MC
V
*T
ON
The
I
L
(
MAX
) term is generated with a bias
current that is proportional to R
PMOS
, to
keep the value of current limit approximately
constant over process and temperature
variations, while the MC
V
*T
ON
is generated
by a peak-holding circuit that senses the
amplitude of the slope compensation ramp
at the end of T
ON
.
There is minimum on-time (T
ON
) generated
even if the COMP node is at zero volts, since
the peak current comparator is reset at the
end of a charge cycle and is held low during
a blanking time after the start of the next
charge cycle. This is necessary to swamp
the transients in the inductor current ramp
around switching times. The minimum T
ON
(50ns, nominally) is not sufficient for the
© 2006 Sipex Corporation
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
5
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