AMI Semiconductor, Inc.
ULP Memory Solutions
670 North McCarthy Blvd. Suite 220
Milpitas, CA 95035
PH: 408-935-7777, FAX: 408-935-7770
N08L163WC2A
8Mb Ultra-Low Power Asynchronous CMOS SRAM
512K × 16 bit
Overview
The N08L163WC2A is an integrated memory
device containing a 8 Mbit Static Random Access
Memory organized as 524,288 words by 16 bits.
The device is designed and fabricated using AMI
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1 and CE2) controls and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently and can also be used to
deselect the device. The N08L163WC2A is optimal
for various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
temperature range of -40
o
C to +85
o
C and is
available in JEDEC standard packages compatible
with other standard 512Kb x 16 SRAMs
Features
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
4.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs(Typical)
• Very low Page Mode operating current
1.0mA at 3.0V and 1µs (Typical)
• Simple memory control
Dual Chip Enables (CE1 and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
25ns OE access time
• Very fast Page Mode access time
t
AAP
= 25ns
• Automatic power down to standby mode
• TTL compatible three-state output driver
• RoHS Compliant
Product Family
Part Number
N08L163WC2AB
N08L163WC2AB2
Package Type
48 - BGA
48 - BGA Green
Operating
Temperature
Power
Supply
(Vcc)
Speed
Standby
Operating
Current (I
SB
), Current (Icc),
Typical
Typical
4
µA
2 mA @ 1MHz
70ns@2.7V
-40
o
C to +85
o
C 2.3V - 3.6V 85ns @ 2.3V
Pin Configuration
1
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
V
SS
V
CC
Pin Descriptions
6
CE2
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
2
OE
UB
I/O
10
I/O
11
I/O
12
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
Pin Name
A
0
-A
18
WE
CE1, CE2
OE
LB
UB
I/O
0
-I/O
15
V
CC
V
SS
NC
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Power
Ground
Not Connected
I/O
14
I/O
13
I/O
15
A
18
NC
A
8
48 Pin BGA (top)
8 x 10 mm
(DOC# 14-02-020 REV G ECN# 01-1281)
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
AMI Semiconductor, Inc.
Functional Block Diagram
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
N08L163WC2A
Address
Inputs
A4 - A18
Page
Address
Decode
Logic
32K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
Word Mux
I/O0 - I/O7
I/O8 - I/O15
CE1
CE2
WE
OE
UB
LB
Control
Logic
Functional Description
CE1
H
X
X
L
L
L
CE2
X
L
X
H
H
H
WE
X
X
X
L
H
H
OE
X
X
X
X
3
L
H
UB
X
X
H
L
1
L
1
L
1
LB
X
X
H
L
1
L
1
L
1
I/O
0
- I/O
151
High Z
High Z
High Z
Data In
Data Out
High Z
MODE
Standby
2
Standby
2
Standby
2
Write
3
Read
Active
POWER
Standby
Standby
Standby
Active
Active
Active
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance
1
Item
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
Min
Max
8
8
Unit
pF
pF
1. These parameters are verified in device characterization and are not 100% tested
(DOC# 14-02-020 REV G ECN# 01-1281)
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
AMI Semiconductor, Inc.
Absolute Maximum Ratings
1
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Soldering Temperature and Time
Symbol
V
IN,OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
N08L163WC2A
Rating
–0.3 to V
CC
+0.3
–0.3 to 4.5
500
–40 to 125
-40 to +85
260
o
C, 10sec
Unit
V
V
mW
o
C
o
C
o
C
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item
Supply Voltage
Data Retention Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Read/Write Operating Supply Current
@ 1
µs
Cycle Time
2
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
Page Mode Operating Supply Current
@ 70ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
Read/Write Quiescent Operating Sup-
ply Current
3
Symbol
V
CC
V
DR
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
OH
= 0.2mA
I
OL
= -0.2mA
V
IN
= 0 to V
CC
OE = V
IH
or Chip Disabled
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
f=0
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 3.6 V
Vcc = 1.8V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
4.0
2.0
9.0
Chip Disabled
3
Test Conditions
Min.
2.3
1.8
1.8
–0.3
V
CC
–0.2
0.2
0.5
0.5
3.0
15.0
V
CC
+0.3
0.6
Typ
1
3.0
Max
3.6
Unit
V
V
V
V
V
V
µA
µA
mA
mA
I
CC3
2.0
3.0
mA
I
CC4
3.0
mA
Maximum Standby Current
3
I
SB1
20.0
µA
Maximum Data Retention Current
3
I
DR
10
µA
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25°C and not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS.
(DOC# 14-02-020 REV G ECN# 01-1281)
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
AMI Semiconductor, Inc.
Power Savings with Page Mode Operation (WE
=
V
IH
)
N08L163WC2A
Page Address (A4 - A18)
Open page
...
Word Address (A0 - A3)
Word 1
Word 2
Word 16
CE1
CE2
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
(DOC# 14-02-020 REV G ECN# 01-1281)
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
AMI Semiconductor, Inc.
Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
N08L163WC2A
0.1V
CC
to 0.9 V
CC
5ns
0.5 V
CC
CL = 30pF
-40 to +85
o
C
Timing
Item
Read Cycle Time
Address Access Time (Random Access)
Address Access Time (Page Mode)
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
Symbol
t
RC
t
AA
t
AAP
t
CO
t
OE
t
LB
, t
UB
t
LZ
t
OLZ
t
LBZ
, t
UBZ
t
HZ
t
OHZ
t
LBHZ
, t
UBHZ
t
OH
t
WC
t
CW
t
AW
t
LBW
, t
UBW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
40
0
5
10
5
10
0
0
0
5
85
50
50
50
40
0
0
20
40
0
5
20
20
20
2.3 - 3.6 V
Min.
85
85
30
85
30
85
10
5
10
0
0
0
5
70
50
50
50
40
0
0
20
20
20
20
Max.
2.7 - 3.6 V
Min.
70
70
25
70
25
70
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(DOC# 14-02-020 REV G ECN# 01-1281)
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
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