CD4072BKMSR datasheet, PDF - EEWORLD Datasheet

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CD4072BKMSR: Description4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDFP14; Categorylogic logic; File Size116KB，10 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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CD4072BKMSR Overview

4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDFP14

CD4072BKMSR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DFP
package instruction	DFP, FL14,.3
Contacts	14
Reach Compliance Code	not_compliant
series	4000/14000/40000
JESD-30 code	R-CDFP-F14
JESD-609 code	e0
length	9.585 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	OR GATE
MaximumI(ol)	0.00036 A
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL14,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
Prop。Delay @ Nom-Sup	338 ns
propagation delay (tpd)	338 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	MIL-PRF-38535 Class V
Maximum seat height	5.33 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
width	6.285 mm

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CD4071BMS, CD4072BMS

CD4075BMS

December 1992

CMOS OR Gate

Pinout

CD4071BMS

TOP VIEW

Features

• High-Voltage Types (20V Rating)

• CD4071BMS Quad 2-Input OR Gate

• CD4072BMS Dual 4-Input OR Gate

• CD4075BMS Triple 3-Input OR Gate

• Medium Speed Operation:

- tPHL, tPLH = 60ns (typ) at 10V

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Standardized Symmetrical Output Characteristics

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

A 1

B 2

J=A+B 3

K=C+C 4

C 5

D 6

VSS 7

14 VDD

13 H

12 G

11 M = G + H

10 L = E + F

9 F

8 E

CD4072BMS

TOP VIEW

J=A+B+C+D 1

A 2

B 3

C 4

14 VDD

13 K = E +F + G + H

12 H

11 G

10 F

9 E

8 NC

Description

CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-

vide the system designer with direct implementation of the

positive-logic OR function and supplement the existing fam-

ily of CMOS gates.

The CD4071BMS, CD4072BMS and CD4075BMS are supplied

in these 14 lead outline packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

*CD4071, CD4072

*H4H

H1B

H3W

†CD4075 Only

†H4Q

D 5

NC 6

VSS 7

NC = NO CONNECTION

CD4075BMS

TOP VIEW

A 1

B 2

D 3

E 4

F 5

K=D+E+F 6

VSS 7

14 VDD

13 G

12 H

11 I

10 L = G + H + I

9 J=A+B+C

8 C

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number

3323

7-444

CD4072BKMSR Related Products

	CD4072BKMSR	CD4072BDMSR	CD4072BFMSR	CD4075BFMSR	CD4071BFMSR	CD4075BKMSR	CD4075BDMSR
Description	4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDFP14	4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDIP14, BRAZE SEALED, DIP-14	4000/14000/40000 SERIES, DUAL 4-INPUT OR GATE, CDIP14, FRIT SEALED, DIP-14	4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14	4000/14000/40000 SERIES, QUAD 2-INPUT OR GATE, CDIP14, FRIT SEALED, DIP-14	4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDFP14, CERAMIC, DFP-14	4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14, BRAZE SEALED, DIP-14
Parts packaging code	DFP	DIP	DIP	DIP	DIP	DFP	DIP
package instruction	DFP, FL14,.3	BRAZE SEALED, DIP-14	FRIT SEALED, DIP-14	DIP, DIP14,.3	DIP, DIP14,.3	DFP, FL14,.3	DIP, DIP14,.3
Contacts	14	14	14	14	14	14	14
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	unknown	not_compliant	not_compliant
series	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000
JESD-30 code	R-CDFP-F14	R-CDIP-T14	R-GDIP-T14	R-GDIP-T14	R-GDIP-T14	R-CDFP-F14	R-CDIP-T14
length	9.585 mm	9.585 mm	9.585 mm	9.585 mm	9.585 mm	9.585 mm	9.585 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE
MaximumI(ol)	0.00036 A	0.00036 A	0.00036 A	0.00036 A	0.00036 A	0.00036 A	0.00036 A
Number of functions	2	2	2	3	4	3	3
Number of entries	4	4	4	3	2	3	3
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DIP	DIP	DIP	DIP	DFP	DIP
Encapsulate equivalent code	FL14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	FL14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	IN-LINE	IN-LINE	IN-LINE	IN-LINE	FLATPACK	IN-LINE
power supply	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V
Prop。Delay @ Nom-Sup	338 ns	338 ns	338 ns	338 ns	338 ns	338 ns	338 ns
propagation delay (tpd)	338 ns	338 ns	338 ns	338 ns	338 ns	338 ns	338 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum seat height	5.33 mm	5.33 mm	5.33 mm	5.33 mm	5.33 mm	5.33 mm	5.33 mm
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	NO	NO	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
width	6.285 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	6.285 mm	7.62 mm
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	-	incompatible	incompatible
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	-	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
JESD-609 code	e0	e0	e0	e0	-	e0	e0
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED

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