B900M24FXX12 datasheet, PDF - EEWORLD Datasheet

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B900M24FXX12: DescriptionDigital Signal Processor, 0-Ext Bit, 80MHz, CMOS, PQCC44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，100 Pages; ManufacturerLSC/CSI; Websitehttps://lsicsi.com

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B900M24FXX12 Overview

Digital Signal Processor, 0-Ext Bit, 80MHz, CMOS, PQCC44

B900M24FXX12 Parametric

Parameter Name	Attribute value
Maker	LSC/CSI
Parts packaging code	QFN
package instruction	,
Contacts	44
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width
barrel shifter	YES
boundary scan	YES
maximum clock frequency	80 MHz
External data bus width
Format	FIXED POINT
Internal bus architecture	SINGLE
JESD-30 code	S-PQCC-J44
low power mode	YES
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

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Advance Data Sheet

July 1999

B900

Baseband Signal Processor

1 Features

2 Description

The B900 is a 16-bit, fixed-point baseband signal

processor based on the DSP1600 core. It is pro-

grammable to perform a wide variety of fixed-point

signal processing functions. A member of the

DSP1600 family, the B900 includes a mix of periph-

erals specifically intended to support processing-

intensive but cost-sensitive applications. In addition

to the core, the B900 consists of the following

peripheral blocks: a programmable phase-locked

loop (PLL), synchronous serial interface unit (SSI),

four I/O ports (IOPs), two timer units, a watchdog

timer, one dual-channel serial I/O interface (SIO), a

JTAG interface, 2 Kwords of RAM, and 24 Kwords of

ROM. The B900 is specifically designed as the core

processor for a low-cost, high-performance cordless

platform. The B900, along with the Lucent Technolo-

gies Microelectronics Group CSP1009 and W9009

devices, provides all of the functionality required for

a digital-cordless application. (Please refer to the

CSP1009 and W9009 data sheets for more informa-

tion.)

The B900 is available in the following packages:

For 5 V operation:

— 12.5 ns instruction cycle time (80 MIPS)

(See Table 89 on page 71.)

For 3.3 V operation:

— 16.7 ns instruction cycle time (60 MIPS)

(See Table 89 on page 71.)

Power-saving features:

— Low-power CMOS technology; fully static

design

— Active power: 9.5 mW/MIPS at 5.0 V;

3.3 mW/MIPS at 3.3 V

— Low-power stopclk: 175 µW at 5.0 V;

— 66 µW at 3.3 V

2 Kwords internal RAM

24 Kwords of internal ROM

16 x 16-bit multiplication and 36-bit accumulation

in one instruction cycle

Two 36-bit accumulators

Instruction cache for high-speed, program-

efficient, zero-overhead looping

One external vectored interrupt

Two 64 Kword address spaces

Programmable phase-locked loop

Three 8-bit and one 4-bit I/O ports for flexible

status or control pins

Two interrupt timers and one watchdog timer

High- and low-frequency clock options

Synchronous serial interface unit

Object code upward compatible with DSP1600

Digital Signal Processor family

Supported by software support tools for both PC

and

UNIX*

platforms

Full-speed in-circuit emulation HDS (HD-

supported)

One dual-channel serial I/O port

One bit manipulation unit

44-pin PLCC (see Figure 1 on page 8)

44-pin MQFP (see Figure 2 on page 9)

The B900 achieves high throughput without pro-

gramming restrictions or latencies due to its parallel

pipelined architecture. The processor has an arith-

metic unit capable of a 16 x 16-bit multiplication and

36-bit accumulation, or a 32-bit ALU operation in

one instruction cycle. Data is accessed from mem-

ory through two independent addressing units.

A fully static, low-power CMOS design and a low-

power standby mode support power-sensitive equip-

ment applications.

UNIX

is a registered trademark of Novell, Inc. licensed

exclusively through X/Open Company Ltd.

B900

Baseband Signal Processor

Advance Data Sheet

July 1999

Table of Contents

Contents

Page

Features ............................................................................................................................................................. 1

Description ......................................................................................................................................................... 1

Pin Information ................................................................................................................................................... 8

Hardware Architecture ..................................................................................................................................... 15

4.1 B900 Architectural Overview .................................................................................................................... 15

4.1.1 DSP1600 Core ................................................................................................................................ 18

4.1.2 Dual-Port RAM (DPRAM) ................................................................................................................ 18

4.1.3 Read-Only Memory (ROM) .............................................................................................................. 18

4.1.4 Timers .............................................................................................................................................. 18

4.1.5 Watchdog Timer .............................................................................................................................. 18

4.1.6 Input/Output Ports (IOP) .................................................................................................................. 18

4.1.7 JTAG ............................................................................................................................................... 18

4.1.8 Synchronous Serial Interface Units (SSI) ........................................................................................ 19

4.1.9 Clock Generation ............................................................................................................................. 19

4.1.10 Dual-Channel Serial I/O Port (SIO) ................................................................................................. 19

4.1.11 Bit Manipulation Unit (BMU) ............................................................................................................ 19

4.2 DSP1600 Core Architectural Overview .................................................................................................... 20

4.2.1 System Cache and Control Section (SYS) ...................................................................................... 22

4.2.2 Data Arithmetic Unit (DAU) .............................................................................................................. 22

4.2.3 Y Space Address Arithmetic Unit (YAAU) ....................................................................................... 22

4.2.4 X Space Address Arithmetic Unit (XAAU) ....................................................................................... 22

4.3 Interrupts, Trap, and Low-Power Standby Mode ...................................................................................... 22

4.3.1 Interruptibility ................................................................................................................................... 23

4.3.2 Vectored Interrupts .......................................................................................................................... 23

4.3.3 External Interrupt Pin (INTB) ........................................................................................................... 23

4.3.4 Clearing Interrupts ........................................................................................................................... 24

4.3.5 Power-Saving Modes ...................................................................................................................... 24

4.4 Memory Maps and Wait-States ................................................................................................................ 24

4.4.1 Instruction/Coefficient Memory Map Selection ................................................................................ 24

4.4.2 Data Memory Map Selection ........................................................................................................... 25

4.5 Clock Generation ...................................................................................................................................... 26

4.5.1 Functional Overview ........................................................................................................................ 26

4.5.2 Core Clock Switching ...................................................................................................................... 28

4.6 Synchronous Serial Interface (SSI) .......................................................................................................... 29

4.6.1 SSI Operation .................................................................................................................................. 30

4.7 I/O Ports (IOP) .......................................................................................................................................... 31

4.7.1 IOP Operation.................................................................................................................................. 31

4.7.2 IOPA Interrupt Circuitry .................................................................................................................... 31

4.7.3 Pin Multiplexing Control .................................................................................................................. 32

4.8 Timers ....................................................................................................................................................... 33

4.9 Watchdog Timer ....................................................................................................................................... 33

4.10 Dual-Channel Serial I/O Port (SIO) for B900 .......................................................................................... 34

4.10.1 B900 SIO Architecture..................................................................................................................... 35

4.10.2 B900 SIO Operation ........................................................................................................................ 36

4.10.3 B900 SIO Programming Examples .................................................................................................. 37

4.11 Bit Manipulation Unit (BMU) .................................................................................................................... 38

Lucent Technologies Inc.

Advance Data Sheet

July 1999

B900

Baseband Signal Processor

Table of Contents

(continued)

Contents

Page

5 Software Architecture ....................................................................................................................................... 39

5.1 Instruction Set ........................................................................................................................................... 39

5.1.1 F1 Multiply/ALU Instructions ............................................................................................................ 39

5.1.2 F2 Special Function Instructions ..................................................................................................... 41

5.1.3 Control Instructions .......................................................................................................................... 42

5.1.4 Conditional Mnemonics (Flags) ....................................................................................................... 43

5.1.5 F3 ALU Instructions ......................................................................................................................... 44

5.1.6 F4 BMU Instructions ........................................................................................................................ 44

5.1.7 Cache Instructions ........................................................................................................................... 47

5.1.8 Data Move Instructions .................................................................................................................... 48

5.2 Register Settings ...................................................................................................................................... 49

5.3 Reset States ............................................................................................................................................ 62

5.4 Instruction Set Formats ............................................................................................................................ 63

5.4.1 Multiply/ALU Instructions ................................................................................................................. 63

5.4.2 Special Function Instructions ........................................................................................................... 63

5.4.3 Control Instructions .......................................................................................................................... 64

5.4.4 Data Move Instructions .................................................................................................................... 65

5.4.5 Cache Instructions ........................................................................................................................... 65

5.4.6 Field Descriptions ............................................................................................................................ 66

6 Device Requirements and Characteristics ....................................................................................................... 70

6.1 Absolute Maximum Ratings ...................................................................................................................... 70

6.2 Handling Precautions ............................................................................................................................... 70

6.3 Recommended Operating Conditions ...................................................................................................... 71

6.4 Decoupling Requirements ........................................................................................................................ 71

6.5 Package Thermal Considerations ............................................................................................................ 71

7 Electrical Requirements and Characteristics ................................................................................................... 72

7.1 Typical Power Dissipation ........................................................................................................................ 74

7.2 Input and I/O Buffer Power Dissipation ..................................................................................................... 76

8 Timing Requirements and Characteristics ....................................................................................................... 77

8.1 Input Clock Options .................................................................................................................................. 77

8.2 B900 Clock Generation ............................................................................................................................ 78

8.3 Reset Synchronization .............................................................................................................................. 79

8.4 JTAG I/O Specifications ........................................................................................................................... 80

8.5 Interrupt ..................................................................................................................................................... 81

8.6 Input/Output Ports (IOP) ........................................................................................................................... 82

8.7 Synchronous Serial Interface (SSI) Specifications ................................................................................... 83

8.8 Serial I/O Specifications ........................................................................................................................... 86

9 Crystal Oscillator Electrical Requirements and Characteristics ....................................................................... 91

9.1 Crystal Oscillator ...................................................................................................................................... 91

9.1.1 Crystal Oscillator Power Dissipation................................................................................................ 91

9.1.2 Crystal Oscillator External Components .......................................................................................... 91

9.1.3 Crystal Oscillator Negative Resistance Curves ............................................................................... 92

9.2 Frequency Accuracy Considerations ........................................................................................................ 94

10 Outline Diagrams ............................................................................................................................................. 97

10.1 44-Pin PLCC ........................................................................................................................................... 97

10.2 44-Pin MQFP .......................................................................................................................................... 98

11 Ordering Information ........................................................................................................................................ 99

11.1 Device Coding ......................................................................................................................................... 99

11.2 Mask-Programmable Options ................................................................................................................. 99

Lucent Technologies Inc.

B900

Baseband Signal Processor

Advance Data Sheet

July 1999

Table of Contents

(continued)

Figure

Page

Figure 1. B900 44-Pin PLCC Pin Diagram ............................................................................................................... 8

Figure 2. B900 44-Pin MQFP Pin Diagram .............................................................................................................. 9

Figure 3. B900 Pinout by Group ............................................................................................................................. 10

Figure 4. B900 Block Diagram................................................................................................................................ 16

Figure 5. DSP1600 Core Block Diagram................................................................................................................ 20

Figure 6. Clock Generation Overview..................................................................................................................... 27

Figure 7. SSI Interconnections ............................................................................................................................... 29

Figure 8. B900 SIO Block Diagram ........................................................................................................................ 35

Figure 9. 64-Bit and 80-Bit Serial Transfer in Active, Single-Channel Mode.......................................................... 36

Figure 10. Plot of V

vs. I

Under Typical Operating Conditions........................................................................ 73

Figure 11. Plot of V

vs. I

Under Typical Operating Conditions ......................................................................... 73

Figure 12. I/O Clock Timing Diagram ..................................................................................................................... 78

Figure 13. Reset Synchronization Timing............................................................................................................... 79

Figure 14. JTAG Timing Diagram........................................................................................................................... 80

Figure 15. Interrupt Timing Diagram....................................................................................................................... 81

Figure 16. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) .................................................. 82

Figure 17. SSI Transfer Timing (SPHA = 0) ........................................................................................................... 83

Figure 18. SSI Transfer Timing (SPHA = 1) ........................................................................................................... 84

Figure 19. SIO Active Output Timing Diagram ....................................................................................................... 86

Figure 20. SIO Passive Output Timing Diagram .................................................................................................... 87

Figure 21. SIO Active Input Timing Diagram .......................................................................................................... 88

Figure 22. SIO Passive Input Timing Diagram ....................................................................................................... 89

Figure 23. Serial I/O Active Clocks Timing Diagram .............................................................................................. 90

Figure 24. Fundamental Crystal Configuration....................................................................................................... 91

Figure 25. 5 V Crystal Oscillator Negative Resistance Curves .............................................................................. 92

Figure 26. 3.3 V Crystal Oscillator Negative Resistance Curves ........................................................................... 93

Figure 27. Components of Load Capacitance for Crystal Oscillator....................................................................... 94

Lucent Technologies Inc.

Advance Data Sheet

July 1999

B900

Baseband Signal Processor

Table of Contents

(continued)

Table

Page

Table 1. B900 Pinout ..............................................................................................................................................

Table 2. B900 Power Supply, Ground, and Unconnected Pins ..............................................................................

Table 3. System Interface.......................................................................................................................................

Table 4. Synchronous Serial Interface (SSI) ..........................................................................................................

Table 5. I/O Port Interface (IOP).............................................................................................................................

Table 6. JTAG Test Mode Interface........................................................................................................................

Table 7. PWR/GND ................................................................................................................................................

Table 8. B900 Block Diagram Legend ....................................................................................................................

Table 9. DOUT Pin Output Functions .....................................................................................................................

Table 10. DSP1600 Core Block Diagram Legend ..................................................................................................

Table 11. Interrupt Vectors .....................................................................................................................................

Table 12. Instruction/Coefficient Memory Map (X Memory Space) ........................................................................

Table 13. Data (Y) Memory Map ............................................................................................................................

Table 14. Clock Options .........................................................................................................................................

Table 15. Clock Switch Latencies...........................................................................................................................

Table 16. Core Clock Stabilization Requirements ..................................................................................................

Table 17. SSI Pin Descriptions ...............................................................................................................................

Table 18. IOP Operation.........................................................................................................................................

Table 19. IOP Pin Multiplexing ...............................................................................................................................

Table 20. SIO Read/Write Pointer Operation .........................................................................................................

Table 21. Instruction Set Operators........................................................................................................................

Table 22. F1 Multiply/ALU Instructions ...................................................................................................................

Table 23. Replacement Table for F1 Multiply/ALU Instructions..............................................................................

Table 24. F2 Special Function Instructions.............................................................................................................

Table 25. Replacement Table for F2 Special Function Instructions .......................................................................

Table 26. Control Instructions.................................................................................................................................

Table 27. Replacement Table for Control Instructions ...........................................................................................

Table 28. B900 Conditional Mnemonics .................................................................................................................

Table 29. F3 ALU Instructions ................................................................................................................................

Table 30. Replacement Table for F3 ALU Instructions...........................................................................................

Table 31. Replacement Table for F4 BMU Instructions..........................................................................................

Table 32. Cache Instructions ..................................................................................................................................

Table 33. Replacement Table for Cache Instructions.............................................................................................

Table 34. Data Move Instructions ...........................................................................................................................

Table 35. Replacement Table for Data Move Instructions......................................................................................

Table 36.

alf

(Standby and Memory Map) Register................................................................................................

Table 37.

auc

(Arithmetic Unit Control) Register....................................................................................................

Table 38.

cbit<a—d>

(IOP Control Bit) and

sbit<a—d>

(IOP Status Bit) Registers .............................................

Table 39.

chipc

Register Fields .............................................................................................................................

Table 40.

chipo

Register Fields .............................................................................................................................

Table 41.

clkc

Register Fields................................................................................................................................

Table 42.

inc

(Interrupt Control) Register...............................................................................................................

Table 43.

ins

(Interrupt Status) Register ................................................................................................................

Table 44. IOPUC<a—d> Register Fields................................................................................................................

Table 45. JTAG ID Register (32-bit) .......................................................................................................................

Table 46. JTAG ROMCODE Letter Values.............................................................................................................

Table 47.

pllc

Register Fields.................................................................................................................................

Table 48.

psw

(Processor Status Word) Register ..................................................................................................

Table 49.

sbit<a—d>

(IOP Status Bit) and

cbit<a—d>

(IOP Control Bit) Registers .............................................

Table 50. SIO Control Register (sioc) Fields .........................................................................................................

Lucent Technologies Inc.

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