a
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
160K Bytes of On-Chip RAM, Configured as 32K Words
Program Memory RAM and 32K Words
Data Memory RAM
Dual Purpose Program Memory for Instruction and Data
Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
DSP Microcomputer
ADSP-2187L
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
32K 24 PM
32K 16 DM
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
(
8K 24 OVERLAY 1
8K 24 OVERLAY 2
) (
8K 16 OVERLAY 1
8K 16 OVERLAY 2
)
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
HOST MODE
ADSP-2100 BASE
ARCHITECTURE
GENERAL NOTE
This data sheet represents specifications for the ADSP-2187L
3.3 V processor.
GENERAL DESCRIPTION
The ADSP-2187L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2187L combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2187L integrates 160K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2187L is available in 100-lead TQFP
package.
In addition, the ADSP-2187L supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2187L operates with a 19 ns instruction cycle time. Ev-
ery instruction can execute in a single processor cycle.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADSP-2187L
The ADSP-2187L’s flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-2187L can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
DEVELOPMENT SYSTEM
•
•
•
•
•
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual
(ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional Information
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2187L. The System Builder provides a high
level method for defining the architecture of systems under de-
velopment. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruc-
tion-level simulation with a reconfigurable user interface to dis-
play different portions of the hardware environment.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2187L assembly source
code. The source code debugger allows programs to be cor-
rected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator, and PROM Splitter soft-
ware. The ADSP-218x EZ-KIT Lite is a low cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite includes the fol-
lowing features:
• 33 MHz ADSP-218x
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort
®
Codec
• RS-232 Interface to PC with Windows 3.1 Control Software
• EZ-ICE
®
Connector for Emulator Control
• DSP Demo Programs
The ADSP-218x EZ-ICE Emulator aids in the hardware debug-
ging of ADSP-2187L system. The emulator consists of hard-
ware, host computer resident software and the target board
connector. The ADSP-2187L integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family
EZ-ICEs. The ADSP-2187L device need not be removed from
the target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector, emu-
lation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
This data sheet provides a general overview of ADSP-2187L
functionality. For additional information on the architecture and
instruction set of the processor, see the
ADSP-2100 Family
User’s Manual, Third Edition.
For more information about the
development tools, refer to the ADSP-2100 Family Develop-
ment Tools Data Sheet.
ARCHITECTURE OVERVIEW
The ADSP-2187L instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2187L assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
POWER-DOWN
CONTROL
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
MEMORY
PROGRAM
SEQUENCER
32K 24 PM
32K 16 DM
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
(
8K 24 OVERLAY 1
8K 24 OVERLAY 2
) (
8K 16 OVERLAY 1
8K 16 OVERLAY 2
)
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
HOST MODE
ADSP-2100 BASE
ARCHITECTURE
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the ADSP-2187L. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
The shifter can be used to efficiently implement numeric for-
mat control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
–2–
REV. 0
ADSP-2187L
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2187L executes looped code with zero over-
head; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2187L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2187L can fetch an operand from program memory and
the next instruction in the same cycle.
In lieu of the address and data bus for external memory connec-
tion, the ADSP-2187L may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR,
BGH,
and
BG).
One execution mode (Go Mode) allows the ADSP-2187L to con-
tinue running from on-chip memory. Normal execution mode re-
quires the processor to halt while buses are granted.
The ADSP-2187L can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET
signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
REV. 0
–3–
The ADSP-2187L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every
n
pro-
cessor cycle, where
n
is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2187L incorporates two complete synchronous se-
rial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2187L
SPORTs. For additional information on Serial Ports, refer to
the
ADSP-2100 Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
µ-law
companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique in-
terrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and
IRQ1)
and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONS
The ADSP-2187L will be available in a 100-lead TQFP pack-
age. In order to maintain maximum functionality and reduce
package size and pin count, some serial port, programmable
flag, interrupt and external bus pins have dual, multiplexed
functionality. The external bus pins are configured during
RESET
only, while serial port pins are software configurable
during program execution. Flag and interrupt functionality is re-
tained concurrently on multiplexed pins. In cases where pin
functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics. See Common-
Mode Pin Descriptions.
ADSP-2187L
Common-Mode Pin Descriptions
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL0/
PF6
IRQL1/
PF5
IRQE/
PF4
Mode D/
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI, FO
PWD
PWDACK
FL0, FL1,
FL2
VDD and
GND
EZ-Port
# of Input/
Pins Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
1
I
I/O
1
I
I/O
1
I
I/O
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Request.
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
2
Power-Down Control Input
Power-Down Control Output
Output Flags
Power and Ground
For Emulation Use
NOTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to en-
able the corresponding interrupts, then the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
Memory Interface Pins
The ADSP-2187L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during
RESET
and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin
# of Input/
Name(s) Pins Output Function
A13:0
14
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
D23:0
24
I/O
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
Host Mode Pins (Mode C = 1)
Pin
Name(s)
IAD15:0
A0
D23:8
IWR
IRD
IAL
IS
IACK
# of
Pins
16
1
16
1
1
1
1
1
Input/
Output Function
I/O
IDMA Port Address/Data Bus
O
Address Pin for External I/O, Pro-
gram, Data or Byte access
I/O
Data I/O Pins for Program, Data
Byte and I/O spaces
I
IDMA Write Enable
I
IDMA Read Enable
I
IDMA Address Latch Pin
I
IDMA Select
O
IDMA Port Acknowledge Configur-
able in Mode D; Open Source
2
1
5
5
I
O
I/O
I/O
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS
and
IOMS
signals
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
I/O
3-State
(Z)
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
Reset
State
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z*
Caused
By
Unused
Configuration
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
1
1
3
16
9
I
O
O
I
I/O
BR,
IS
BR,
BR,
BR,
EBR
EBR
EBR
EBR
–4–
REV. 0
ADSP-2187L
D6 or
IRD
D5 or
IAL
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
**
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
**
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
BR, EBR
Float
BR, EBR
High (Inactive)
Float
Low (Inactive)
BR, EBR
Float
High (Inactive)
BR, EBR
Float
**
BR, EBR
Float
IS
Float
BR, EBR Float
BR, EBR
Float
BR, EBR
Float
BR, EBR
Float
BR, EBR
Float
BR, EBR
Float
BR, EBR
Float
High (Inactive)
EE
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let them
float.
3. All bidirectional pins have three-stated outputs. When the pins is configured as
an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
Interrupts
IRQL0/PF6
I/O (Z)
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2187L provides four dedicated external interrupt
input pins,
IRQ2, IRQL0, IRQL1
and
IRQE.
In addition,
SPORT1 may be reconfigured for
IRQ0, IRQ1,
FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2187L also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0
and
IRQ1
input pins can be programmed to be
either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-
sensitive and
IRQE
is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
I
IRQL1/PF5
I/O (Z)
I
Source of Interrupt
RESET
(or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer
Interrupt Vector
Address (Hex)
0000 (Highest
Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest
Priority)
IRQE/PF5
I/O (Z)
I
SCLK0
RFS0
DR0
TFS0
DT0
SCLK1
RFS1/RQ0
DR1/FI
TFS1/RQ1
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I/O
I/O
I
I/O
O
I/O
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
I
O
O
I
I
I
O
O
I
I
O
I
O
I
I
I
O
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Indi-
vidual interrupt requests are logically ANDed with the bits in
IMASK; the highest priority unmasked interrupt is then se-
lected. The power-down interrupt is nonmaskable.
The ADSP-2187L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port auto-
buffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the
IRQ0, IRQ1
and
IRQ2
external interrupts to
be either edge- or level-sensitive. The
IRQE
pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0
and
IRQL1
pins are external level-sensitive interrupts.
NOTES
**Hi-Z
= High Impedance.
**Determined by MODE D pin:
Mode D = 0 and in host mode:
IACK
is an active, driven signal and cannot be
“wire ORed.” If unused, let float.
Mode D = 1 and in host mode:
IACK
is an open source and requires an exter-
nal pull-down, but multiple
IACK
pins can be “wire ORed” together. If un-
used, let float.
1. If the CLKOUT pin is not used, turn it OFF.
REV. 0
–5–
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