feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128 is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin Configurations
Top View
SOIC
NC
A
16
A
14
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT
BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x 256x 8
ARRAY
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
ROW DECODER
CE
1
CE
2
WE
OE
A
4
A
5
A
6
A
7
A
12
A
14
A
16
NC
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
62128-1
TSOP I
Reverse Pinout
Top View
(not to scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
62128-2
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
A
10
OE
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I/ STSOP
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
62128-2
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
July 1996 - Revised June 18, 1998
CY62128
Selection Guide
CY62128-55
Maximum Access Time (ns)
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
Commercial
L
LL
L
LL
55
50
50
80
15
CY62128-70
70
40
40
80
15
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
2
CY62128
Electrical Characteristics
Over the Operating Range
62128–55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Cur-
rent
Output Short Circuit
Current
[4]
V
CC
Operating
Supply Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
L
LL
Ind.’l
L
LL
I
SB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. V
CC
,
CE
1
≥
V
IH
or CE
2
< V
IL
,
V
IN
≥
V
IH
or
V
IN
≤
V
IL
, f = f
MAX
Com’l
L
LL
Ind.’l
L
LL
I
SB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
CC
,
CE
1
≥
V
CC
– 0.3V,
or CE
2
≤
0.3V,
V
IN
≥
V
CC
– 0.3V,
or V
IN
≤
0.3V, f=0
Com’l
L
LL
Ind
L
LL
0.4
0.4
40
30
30
40
30
30
0.3
0.15
0.1
0.3
0.15
0.1
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 2.1mA
2.2
–0.3
–1
+1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
115
70
70
115
70
70
25
3
2
25
3
2
500
100
20
500
100
40
0.4
0.4
40
30
30
40
30
30
0.3
0.15
0.1
0.3
0.15
0.1
2.2
–0.3
–1
+1
Typ
[3]
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
110
60
60
110
70
70
1
1
1
1
1
1
500
100
20
500
100
40
62128–70
Typ
[3]
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
9
9
Unit
pF
pF
Notes:
3. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at V
CC
= 5.0V, T
A
= 25°C, and t
AA
=70ns
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
3
CY62128
AC Test Loads and Waveforms
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R1 1800
Ω
R1 1800
Ω
5V
OUTPUT
R2
990
Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
990
Ω
GND
≤
5ns
3.0V
90%
10%
90%
10%
≤
5 ns
ALL INPUT PULSES
62128-3
62128-4
THÉVENIN EQUIVALENT
639
Ω
1.77V
OUTPUT
Switching Characteristics
[6]
Over the Operating Range
62128–55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7,8]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[8]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[7,8]
62128–70
Min.
70
Max.
Unit
ns
70
5
70
35
0
25
5
25
0
70
70
60
60
0
0
50
30
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
Description
Min.
55
Max.
55
5
55
20
0
20
5
20
0
55
55
45
45
0
0
45
25
0
5
20
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[8]
WE LOW to High Z
[7, 8]
WRITE CYCLE
[9]
Notes:
6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100pF load capacitance.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
4
CY62128
Data Retention Characteristics
(Over the Operating Range for “L” and “LL” version only)
[i=s]This post was last edited by yuanlai2010 on 2014-9-2 13:12[/i] [align=center][b][color=#0070C0][font=华文楷体][size=22.0pt]System V IPC [/size][/font][/color][/b][b][font=华文楷体][size=22.0pt]–[/size][/...
I have a question for you: When using it as a 24-bit RGB LCD, except for PB0 which uses the AF9 function of the pin, all other pins use the AF14 function. Is this possible?...
[color=#333333]IAR 5.3 for 430, why do I get a warning when the value of the operation assignment exceeds 40000 even though I assign the value directly? The value assigned by the operation cannot be u...
PCB Design
京公网安备 11010802033920号
EEWORLD
