EEWORLDEEWORLDEEWORLD

Part Number

Search

86834-326

Description
Board Connector, 26 Contact(s), 2 Row(s), Male, Straight, Solder Terminal
CategoryThe connector    The connector   
File Size614KB,8 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

86834-326 Overview

Board Connector, 26 Contact(s), 2 Row(s), Male, Straight, Solder Terminal

86834-326 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAmphenol
Reach Compliance Codecompliant
Connector typeBOARD CONNECTOR
Contact to complete cooperationGOLD (50) OVER NICKEL (50)/GOLD FLASH (50) OVER PALLADIUM NICKEL
Contact completed and terminatedGOLD (50) OVER NICKEL (50)/GOLD FLASH (50) OVER PALLADIUM NICKEL
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
DIN complianceNO
Filter functionNO
IEC complianceNO
JESD-609 codee4
MIL complianceNO
Manufacturer's serial number86834
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded2
OptionsGENERAL PURPOSE
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts26
UL Flammability Code94V-0
PDM: Rev:DF
STATUS:
Released
Printed: Jun 02, 2011
.
[I contribute to the Xilinx Resource Center] A large amount of Verilog source code
A lot of Verilog source codeVerilog HDL 程序举例 一,基本组合逻辑功能: 双向管脚(clocked bidirectional pin) Verilog HDL: Bidirectional PinThis example implements a clocked bidirectional pin in Verilog HDL. The value of ...
wanghongyang FPGA/CPLD
Homemade USBISP download cable
...
qin552011373 DIY/Open Source Hardware
Slow display speed
Why does the display speed slow down after I turn on the "average sampling" mode or set a longer persistence time when using Dingyang oscilloscope?...
lily608487 Test/Measurement
Scattered: Can ITU656 data without VSYNC/HREF trigger the CAMERA interrupt of S3C6410?
Can ITU656 data without VSYNC/HREF trigger the S3C6410 CAMERA interrupt? How to configure the S3C6410 CAMERA interface? What are the requirements for the CAMERA input? Can it be the standard 720*576 P...
eekingking Embedded System
My Beaglebone learning journey
Organize the previous posts and make a general post to facilitate communication.1. BeagleBone Hardware Performance Test_Weekly Planhttps://bbs.eeworld.com.cn/thread-324885-1-1.html 2. BeagleBone hardw...
chenzhufly DSP and ARM Processors
How to solve the glitch
[font=黑体][size=5]vcc is a fixed level I set, q1 is a sine wave generated by counter + rom, alb is the output waveform after vcc and q1 pass through the comparator, q1 No code? How to solve the glitch...
xmllf FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2624  94  396  2064  2010  53  2  8  42  41 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号