AT28BV256-20TL datasheet, PDF - EEWORLD Datasheet

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AT28BV256-20TL: DescriptionEEPROM, 32KX8, 200ns, Parallel, CMOS, PDSO28, 8 X 13.40 MM, PLASTIC, MO-183, TSOP1-28; Categorystorage storage; File Size304KB，18 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT28BV256-20TL Overview

EEPROM, 32KX8, 200ns, Parallel, CMOS, PDSO28, 8 X 13.40 MM, PLASTIC, MO-183, TSOP1-28

AT28BV256-20TL Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	TSOP1,
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	200 ns
Other features	AUTOMATIC WRITE
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	11.8 mm
memory density	262144 bit
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.55 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	8 mm
Maximum write cycle time (tWC)	10 ms

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Features

•

Single 2.7V - 3.6V Supply

•

Fast Read Access Time – 200 ns

•

Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

– Internal Control Timer

Fast Write Cycle Times

– Page Write Cycle Time: 10 ms Maximum

– 1- to 64-byte Page Write Operation

Low Power Dissipation

– 15 mA Active Current

– 20 µA CMOS Standby Current

Hardware and Software Data Protection

Data Polling for End of Write Detection

High Reliability CMOS Technology

– Endurance: 10,000 Cycles

– Data Retention: 10 Years

JEDEC Approved Byte-wide Pinout

Commercial and Industrial Temperature Ranges

Green (Pb/Halide-free) Packaging Option

•

256K (32K x 8)

Battery-Voltage

Parallel

EEPROMs

AT28BV256

•

1. Description

The AT28BV256 is a high-performance electrically erasable and programmable read-

only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-

tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access

times to 200 ns with power dissipation of just 54 mW. When the device is deselected,

the CMOS standby current is less than 200 µA.

The AT28BV256 is accessed like a Static RAM for the read or write cycle without the

need for external components. The device contains a 64-byte page register to allow

writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to

64 bytes of data are internally latched, freeing the address and data bus for other

operations. Following the initiation of a write cycle, the device will automatically write

the latched data using an internal control timer. The end of a write cycle can be

detected by Data polling of I/O7. Once the end of a write cycle has been detected a

new access for a read or write can begin.

Atmel’s AT28BV256 has additional features to ensure high quality and manufactura-

bility. The device utilizes internal error correction for extended endurance and

improved data retention characteristics. An optional software data protection mecha-

nism is available to guard against inadvertent writes. The device also includes an

extra 64 bytes of EEPROM for device identification or tracking.

0273I–PEEPR–7/05

5. Device Operation

5.1

Read

The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins is asserted on the outputs.

The outputs are put in the high impedance state when either CE or OE is high. This dual-line

control gives designers flexibility in preventing bus contention in their system.

5.2

Byte Write

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write

cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-

cally time itself to completion. Once a programming operation has been initiated and for the

duration of t

, a read operation will effectively be a polling operation.

5.3

Page Write

The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the

device during a single internal programming period. A page write operation is initiated in the

same manner as a byte write; the first byte written can then be followed by 1 to 63 additional

bytes. Each successive byte must be written within 150 µs (t

BLC

) of the previous byte. If the t

BLC

limit is exceeded the AT28BV256 will cease accepting data and commence the internal pro-

gramming operation. All bytes during a page write operation must reside on the same page as

defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page

write operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes

may be loaded in any order and may be altered within the same load period. Only bytes which

are specified for writing will be written; unnecessary cycling of other bytes within the page does

not occur.

5.4

Data Polling

The AT28BV256 features Data Polling to indicate the end of a write cycle. During a byte or page

write cycle, an attempted read of the last byte written will result in the complement of the written

data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all

outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write

cycle.

5.5

Toggle Bit

In addition to Data Polling, the AT28BV256 provides another method for determining the end of

a write cycle. During the write operation, successive attempts to read data from the device will

result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-

gling and valid data will be read. Reading the toggle bit may begin at any time during the write

cycle.

5.6

Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system

power supply. Atmel has incorporated both hardware and software features that will protect the

memory against inadvertent writes.

AT28BV256

0273I–PEEPR–7/05

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