P113SD Series 5.0 V
CMOS Clock Oscillators
July 2007
Pletronics Inc. certifies this device is in accordance with the
RoHS (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 4.0 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e1 or e2
Absolute Maximum Ratings:
Parameter
V
CC
Supply Voltage
Vi
Input Voltage
DI
Inc.
SC
Vo
Output Voltage
Thermal Characteristics
The maximum die or junction temperature is 155
o
C
The thermal resistance junction to board is 120
o
C/Watt depending on the solder pads, ground plane and
construction of the PCB.
ON
Unit
-0.5V to +7.0V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
Copyright © 2005, 2006, 2007 Pletronics
Product informatin is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necesarily include testing of all parameters.
TI
NU
E
•
•
•
• Pletronics’ P113SD Series is a quartz crystal
controlled precision square wave generator
with a CMOS output.
• The P113SD series will directly interface TTL
devices also.
• Greatly reduces RFI and EMI system sensitivity
• Minimizes RFI radiation, eases meeting FCC
Class B emissions standards.
• Capable of driving up to 30pF capacitive loads
• Tube packaging is available.
•
•
D
•
•
•
•
70 to 107 MHz
Full Size Thru-Hole DIP package
Enable/Disable Function
Disable function includes low standby power
mode
3
rd
Overtone Crystals used
Improved circuit to minimize oscillator issues
such as multi-mode output signal.
Low Jitter
Has internal bypass capacitor on the Vcc lead
5x7 mm LCC ceramic oscillator inside
P113SD Series 5.0 V
CMOS Clock Oscillators
July 2007
Part Number:
P11
45
-3SD
ES
-100.0M
-30
-XX
Internal code or blank
Marking
TI
Frequency Stability
45
= + 50 ppm
_
44
= + 25 ppm
_
20
= + 20 ppm
_
Series Model
Part Marking:
DI
SC
www.pletronics.com
PLE
P3Sxss
fff.fff
M
yywwaLF
Pletronics may ship the following combinations without notice (this is an enhanced specified device)
44 (25 ppm) stability parts when 45 (50 ppm) was ordered
20 (20 ppm) stability parts when 45 (50 ppm) or 44 (25 ppm) was ordered.
E temperature range parts when extended was not ordered.
S symmetry parts when 40/60% symmetry was ordered.
Pletronics may ship parts that are not marked for extended temperature range but were tested for
extended temperature range, a Certificate of Conformance will accompany these parts.
ON
Where:
x
ss
fff.fff
yywwa
LF
425-776-1880
NU
E
Frequency in MHz
fff.fff
M
none
Supply Voltage V
CC
Blank
= 5.0V _ 10%
+
Enhanced Specifications
(apply in the order shown)
E
= Temperature range -40 to 85
o
C
S
= Symmetry 45%/55% at 50% of V
CC
Series Model
E
S
5
4
2
P3S
= Frequency stability
= Enhanced specification
= Frequency in MHz
= Date code
= Lead Free
(Voltage not shown)
2
Output Load Capacitance
Blank
= 15pF maximum
30
= 30pF maximum
D
none
P113SD Series 5.0 V
CMOS Clock Oscillators
July 2007
Electrical Specification for 5.00V _10% over the specified temperature range
+
Item
Frequency Range
Frequency Accuracy
“45"
“44"
“20"
Output Waveform
Output High Level
Output Low Level
Output Symmetry
0.5
-
40
45
Jitter
-
Min
70
-50
-25
-20
Max
107
+50
+25
+20
CMOS
-
0.4
60
55
1
Unit
MHz
ppm
For all supply voltages, load changes, aging for 1
year, shock, vibration and temperatures
Condition
Enable/Disable Internal Pull-up
V disable
V enable
Output leakage
V
OUT
= V
CC
Enable time
Disable time
SC
Start up time
-
10
Operating Temperature Range
0
+70
-40
+85
Storage Temperature Range
-55
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ON
-10
+10
uA
V
OUT
= 0V
-10
-
+10
100
uA
nS
-
100
nS
mS
o
TI
-
4
-
pS RMS
Kohm
V
50
-
to V
CC
0.5
-
Applied to pad 1
2.0
V
Applied to pad 1
Pad 1 low, device disabled
C
C
C
o
pS RMS
+125
DI
425-776-1880
NU
E
V
Below V
CC
(See load circuit)
V
(See load circuit)
%
at 50% point of V
CC
for “S” option parts
(See load circuit) Standard
%
12 KHz to 20 MHz from the output frequency
10 Hz to 1 MHz from the output frequency
Time for output to reach a logic state
Time for output to reach a high Z state
Time for output to reach specified frequency
Standard Temperature Range
Extended Temperature Range
“E” Option
o
D
3
P113SD Series 5.0 V
CMOS Clock Oscillators
July 2007
Electrical Specification for 5.00V _10% over the specified temperature range
+
Item
V
OUT
High (V
OH
)
V
OUT
Low (V
OL
)
Output T
RISE
and T
FALL
Min
0.5
-
-
-
V
CC
Supply Current
(I
CC
)
-
-
-
-
Typ
0.3
0.3
2.0
3.0
50
45
60
50
Max
-
0.4
4.0
6.0
90
80
100
100
Unit
V
V
nS
nS
Condition
Below V
CC
, I
OH
= +16 mA
I
OL
= -16 mA
C
LOAD
= 15 pF,
mA
mA
mA
mA
Load Circuit and Test Waveform
ON
425-776-1880
SC
www.pletronics.com
DI
TI
Symmetry
Specifications with Pad 1 E/D open circuit
NU
E
C
LOAD
=30 pF,
>100 MHz
<=100 MHz
>100 MHz
C
LOAD
= 15 pF
10% to 90% of V
CC
(See load circuit)
C
LOAD
= 30 pF
10% to 90% of V
CC
(See load circuit)
<=100 MHz
Vhigh
90% * Vcc
50% * Vcc
10% * Vcc
Vlow
Ground
Trise
Tfall
D
4
P113SD Series 5.0 V
CMOS Clock Oscillators
July 2007
Reliability
: Environmental Compliance
Parameter
Mechanical Shock
Vibration
Solderability
Thermal Shock
Condition
MIL-STD-883 Method 2002, Condition A
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Human Body Model
Charged Device Model
Minimum Voltage
1500
1000
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Bar code is 39-Full ASCII
DI
SC
PCB Mounting (typical for lead free processing)
Hand soldering is recommended.
Wave solder at 255
o
C to 280
o
C with maximum wave exposure of 15 seconds
Reflow solder maximum exposure of 245
o
C for 15 seconds
Soldering done in a nitrogen atmosphere enhances the solder joint quality.
www.pletronics.com
425-776-1880
ON
5
TI
NU
E
Conditions
MIL-STD-883 Method 3115
JESD 22-C101
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
D
Embedded System
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