Low Skew, 1-to-2, Differential-to-CML
Fanout Buffer
ICS855S011I
DATA SHEET
General Description
The ICS855S011I is a low skew, high performance 1-to-2,
Differential-to-CML Fanout Buffer. The ICS855S011I is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and part-to-part skew characteristics make the
ICS855S011I ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
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Two differential CML outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Translates any single ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Additive phase jitter, RMS: 0.037ps (typical)
Output skew: 25ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation delay: 375ps (maximum)
Operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK
Pulldown
nPCLK
Pullup/Pulldown
Q0
nQ0
Q1
nQ1
Pin Assignment
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
CC
PCLK
nPCLK
V
EE
ICS855S011I
8-Lead TSSOP
3.0mm x 3.0mm x 0.95mm package body
G Package
Top View
ICS855S011AGI REVISION A NOVEMBER 22, 2010
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©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
nPCLK
PCLK
V
CC
Output
Output
Power
Input
Input
Power
Pullup/Pulldown
Pulldown
Type
Description
Differential output pair. CML interface levels.
Differential output pair. CML interface levels.
Negative supply pin.
Inverting LVPECL differential clock input. Default to
2
/
3
V
CC
when left floating.
Non-inverting LVPECL differential clock input.
Power supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
75
37
Maximum
Units
k
Ω
k
Ω
ICS855S011AGI REVISION A NOVEMBER 22, 2010
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©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.5V (CML mode, V
EE
= 0V)
-0.5V to V
DD
+ 0.5V
20mA
40mA
145.4°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.8V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
52
Units
V
mA
Table 3B. LVPECL Differential DC Characteristics,
V
CC
= 2.375V to 3.8V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High Current
PCLK,
nPCLK
PCLK
I
IL
Input Low Current
nPCLK
V
PP
V
CMR
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Test Conditions
V
CC
= V
IN
= 2.625V or 3.8V
V
CC
= 2.625V or 3.8V,
V
IN
= 0V
V
CC
= 2.625V or 3.8V,
V
IN
= 0V
-10
-150
150
1.2
1200
V
CC
Minimum
Typical
Maximum
150
Units
µA
µA
µA
mV
V
NOTE 1: Common mode input voltage is defined as V
IH
.
Table 3C. CML DC Characteristics,
V
CC
= 2.375V to 3.8V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OUT
V
DIFF_OUT
R
OUT
Parameter
Output High Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage
Swing
Output Source Impedance
Test Conditions
Minimum
V
CC
- 0.020
325
650
40
Typical
V
CC
- 0.010
400
800
50
60
Maximum
V
CC
Units
V
mV
mV
Ω
NOTE 1: Outputs terminated with 50
Ω
to V
CC
.
ICS855S011AGI REVISION A NOVEMBER 22, 2010
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©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics,
V
CC
= 2.375V to 3.8V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
60
47
156.25MHz @ 3.3V, Integration Range:
12kHz – 20MHz
175
0.037
25
200
250
53
Test Conditions
Minimum
Typical
Maximum
2
375
Units
GHz
ps
ps
ps
ps
ps
%
NOTE: All parameters characterized at
≤
1.2GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between different devices operating at the same supply voltage, same frequency, same temperature and with equal
load conditions. Using the same type of inputs on each device, the output is measured at the differential cross point.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS855S011AGI REVISION A NOVEMBER 22, 2010
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©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.037ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator used is, "Rohde & Schwarz SMA100 through
the Hewlett Packard 8133A Generator".
ICS855S011AGI REVISION A NOVEMBER 22, 2010
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©2010 Integrated Device Technology, Inc.
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