K4H560438D-TCB3 datasheet, PDF

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K4H560438D-TCB3: DescriptionDDR DRAM, 64MX4, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66; Categorystorage storage; File Size235KB，25 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4H560438D-TCB3 Overview

DDR DRAM, 64MX4, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66

K4H560438D-TCB3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2, TSSOP66,.46
Contacts	66
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
JESD-609 code	e0
length	22.22 mm
memory density	268435456 bit
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	66
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.003 A
Maximum slew rate	0.29 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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256Mb

Key Features

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• LDM,UDM/DM for write masking only

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

• 66pin TSOP II package

DDR SDRAM

ORDERING INFORMATION

Part No.

K4H560438D-TC/LB3

K4H560438D-TC/LA2

K4H560438D-TC/LB0

K4H560438D-TC/LA0

K4H560838D-TC/LB3

K4H560838D-TC/LA2

K4H560838D-TC/LB0

K4H560838D-TC/LA0

K4H561638D-TC/LB3

K4H561638D-TC/LA2

K4H561638D-TC/LB0

K4H561638D-TC/LA0

16M x 16

32M x 8

64M x 4

Org.

Max Freq.

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

A0(DDR200@CL=2)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

A0(DDR200@CL=2)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

A0(DDR200@CL=2)

SSTL2

66pin TSOP II

SSTL2

66pin TSOP II

SSTL2

66pin TSOP II

Interface

Package

Operating Frequencies

- B3(DDR333)

Speed @CL2

Speed @CL2.5

133MHz

166MHz

- A2(DDR266A)

133MHz

- B0(DDR266B)

100MHz

133MHz

- A0(DDR200)

100MHz

*CL : Cas Latency

- 1 -

Rev. 0.4 May. 2002

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