MIC58P42
Micrel
MIC58P42
8-Bit Serial-Input Protected Latched Driver
General Description
The MIC58P42 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common STROBE, CLOCK, SERIAL DATA INPUT, and
OUTPUT ENABLE functions. Similar to the MIC5842, addi-
tional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and over-
current shutdown.
The bipolar/CMOS combination provides an extremely low-
power latch with maximum interface flexibility. The MIC58P42
has open-collector outputs capable of sinking 500 mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.
With a 5V logic supply, the MIC58P42 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.
Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current detection, the
affected channel will turn OFF until V
DD
is cycled or the
ENABLE/RESET pin is pulsed high. Current pulses less than
2µs will not activate current shutdown. Temperatures above
165°C will shut down the device. The UVLO circuit prevents
operation at low V
DD
; hysteresis of 0.5V is provided. See the
MIC59P60 for a similar device that additionally provides an
error flag output.
Features
•
•
•
•
•
•
•
•
•
•
3.3 MHz Minimum Data-Input Rate
CMOS, PMOS, NMOS, and TTL Compatible
Internal Pull-Up/Pull-Down Resistors
Low Power CMOS Logic and Latches
High Voltage (80V) Current-Sink Outputs
Output Transient-Protection Diodes
Single or Split Supply Operation
Thermal Shutdown
Under-Voltage Lockout
Per-Output Over-Current Shutdown (500mA typical)
Ordering Information
Part Number
MIC58P42AJ
MIC58P42AJB†
MIC58P42BN
MIC58P42BV
MIC58P42BWM
Temperature Range
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
18-Pin Ceramic DIP
18-Pin Ceramic DIP
18-Pin Plastic DIP
20-Pin PLCC
18-Pin Wide SOIC
† AJB indicates units screened to MIL-STD 883, Method 5004, condition
B, and burned-in for 1 week.
Functional Diagram
Pin Configuration
(Ceramic and Plastic DIP and SOIC)
VEE
1
SUB
18 OUT 1
17 OUT 2
SHIFT REGISTER
CLOCK
SERIAL
DATA IN
2
6
3
8-BIT SERIAL–PARALLEL SHIFT REGISTER
5
VDD
SERIAL DATA OUT
CLOCK
SERIAL DATA IN
VSS
VDD
SERIAL DATA OUT
STROBE
OUTPUT
ENABLE/RESET
2
3
4
5
6
7
8
9
SUB
UVLO
I LIMIT
THERMAL
SHUTDOWN
16 OUT 3
LATCHES
VSS
4
LATCHES
7
STROBE
15 OUT 4
14 OUT 5
13 OUT 6
12 OUT 7
11 OUT 8
10 K
UVLO
MOS
BIPOLAR
8
OUTPUT
ENABLE/RESET
THERMAL
SHUTDOWN
ILIMIT
10
K
18
OUT 1
17
16
15
OUT 4
14
OUT 5
13
OUT 6
12
OUT 7
11
OUT 8
SUB
1
VEE
9
VEE
OUT 2 OUT 3
8-34
MIC58P42
Micrel
PLCC Pin Configuration
SERIAL DATA IN
Absolute Maximum Ratings (Note 1, 2)
at 25°C Free-Air Temperature and V
SS
= 0V
Output Voltage
Output Voltage, V
CE(SUS)
(Note 1)
Logic Supply Voltage Range, V
DD
V
DD
with Reference to V
EE
Emitter Supply Voltage (Substrate), V
EE
Input Voltage Range, V
IN
Package Power Dissipation, P
D
MIC58P42BN
Derate above T
A
= +25°C
MIC58P42AJ/AJB
Derate above T
A
= +25°C
MIC58P42BV
Derate above T
A
= +25°C
MIC58P42BWM
Derate above T
A
= +25°C
Operating Temperature Range, T
A
Storage Temperature Range, T
S
Note 1: For Inductive load applications.
Note 2: CMOS devices have input-static protection but are susceptible to
damage when exposed to extremely high static electrical
charges.
3
2
1
20
19
18
17
80V
50V
4.5V to 15V
25V
–20V
–0.3V to V
DD
+ 0.3V
1.82W
18mW/°C
1.6W
16mW/°C
1.4W
14mW/°C
1.2W
12mW/°C
–55°C to +125°C
–65°C to +150°C
CLOCK
OUT 1
OUT 2
VEE
NC
VSS
VDD
SERIAL DATA OUT
NC
4
5
6
7
8
9
10
11
12
13
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
MIC58P42BV
16
15
14
OE/RESET
STROBE
Typical Input Circuits
V DD
OUT 8
VEE
K
Typical Output Driver
V DD
K
OUT N
STROBE
OUTPUT
ENABLE
CLOCK
SERIAL
DATA IN
3K
V SS
V SS
V EE
SUB
Pin Description
Pin
(DIP & S.O.)
1,9
2
3
4
5
6
7
8
10
11—18
V
EE
CLOCK
SERIAL DATA IN
V
SS
V
DD
SERIAL DATA OUT
STROBE
OUTPUT
ENABLE/RESET
K
OUTPUT N
Substrate. Most Negative voltage in the system connects here.
Serial Data Clock. A CLEAR input must also be clocked into the latches.
Serial Data Input pin.
Logic reference (Ground) pin.
Logic Positive Supply voltage.
Serial Data Output pin. (Flow–through).
Output Strobe pin. Loads output latches when high. Strobe is needed to clear latch.
When Low, Outputs are active. When High, device is reset from a fault condition.
Transient suppression diode's cathode common pin.
Open Collector outputs 8 through 1.
Name
Description
8
8-35
MIC58P42
Micrel
Electrical Characteristics
at T
A
= +25°C, V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Output Leakage Current
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
OUT
= 80V
V
OUT
= 80V, T
A
= +70°C
Collector-Emitter
Saturation Voltage
Collector-Emitter
Sustaining Voltage
Input Voltage
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA
I
OUT
= 350mA, L = 2mH
50
1.0
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V,
Note 1
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
One Driver ON, All others OFF, V
DD
= 12V
One Driver ON, All others OFF, V
DD
= 10V
One Driver ON, All others OFF, V
DD
= 5V
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 10V
All Drivers OFF, V
DD
= 5.0V
V
R
= 80V
I
F
= 350mA
1.7
500
Note 2
3.5
3.0
4.0
3.5
165
10
4.5
4.0
50
50
50
10.5
8.5
3.5
200
300
600
6.4
6.0
4.6
3.1
2.9
2.3
2.6
2.4
1.9
10.0
9.0
7.5
4.5
4.5
3.6
4.2
3.6
3.0
50
2.0
µA
V
mA
V
V
°C
°C
kΩ
0.9
1.1
1.3
Min.
Typ.
Max.
50
100
1.1
1.3
1.6
V
Unit
µA
V
CE(SUS)
V
IN(0)
V
IN(1)
V
V
Input Resistance
R
IN
Supply Current
I
DD(ON)
mA
I
DD (1 ON)
I
DD(OFF)
Clamp Diode
Leakage Current
Clamp Diode
Forward Voltage
Output Current
Shutdown Threshold
Start Up Voltage
Minimum Supply (V
DD
)
Thermal Shutdown
Thermal Shutdown Hysteresis
I
R
V
F
I
LIM
V
SU
V
DD MIN
Note 1:
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
Note 2:
Undervoltage Lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V.
8-36
MIC58P42
Micrel
CLOCK
A
B
DATA IN
E
STROBE
C
F
D
OUTPUT
ENABLE
G
OUT N
Timing Conditions
(T
A
= +25°C, Logic Levels are V
DD
and V
SS
), V
DD
= 5V
A.
B.
C.
D.
E.
F.
G.
Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns
Minimum Data Active Time After Clock Pulse (Data Hold Time).............................................................................. 75 ns
Minimum Data Pulse Width..................................................................................................................................... 150 ns
Minimum Clock Pulse Width ................................................................................................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns
Minimum Strobe Pulse Width .................................................................................................................................. 100 ns
Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OUTPUT ENABLE/
RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and require no reset pulse.
8
MIC58P42 Truth Table
Shift Register Contents
Serial Data
Input
H
L
X
Clock
Input
I
1
H
L
R1
O
X
P
1
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
I
2
R
1
R
1
R2
O
X
P
2
I
3
……
R
2
……
R
2
……
R
3
……
O ……
X ……
P
3
……
I
8
R
7
R
7
R
8
O
X
P
8
Serial
Data
Output
R
7
R
7
R
8
L
X
P
8
Latch Contents
Strobe
Input
I
1
I
2
I
3
……
Output Contents
Output
I
8
Enable I
1
I
2
I
3
…… I
8
L
H
R
1
R
2
P
1
P
2
X
X
R
3
P
3
X
……
……
……
R
8
P
8
X
L
H
P
1
H
P
2
H
P
3
……P
8
H
…… H
8-37
MIC58P42
Micrel
Typical Characteristic Curves
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
–50
0
50
100
TEMPERATURE (°C)
150
V
DD
= 5V to 12V
I
L
= 100mA
Output Saturation
Voltage vs. Temperature
SUPPLY CURRENT (mA)
5
4
3
2
1
0
–50
Supply Current
vs. Temperature
ALL OUTPUTS ON
V
DD
= 5V
SHUTDOWN THRESHOLD (A)
Current Shutdown
Threshold vs. Temperature
0.60
0.55
V
DD
= 5V
0.50
0.45
0.40
0.35
–50
V
DD
= 12V
SATURATION VOLTAGE (V)
I
L
= 350mA
ALL OUTPUTS OFF
0
50
100
TEMPERATURE (°C)
150
0
50
100
TEMPERATURE (°C)
150
300
Output Delay
vs. Supply Voltage
SUPPLY CURRENT (mA)
R
L
= 50Ω
7
6
5
4
3
2
1
0
–50
Supply Current
vs. Temperature
CURRENT LIMIT DELAY (µs)
150
ALL OUTPUTS ON
V
DD
= 12V
20
18
16
14
12
Current Shutdown
Delay vs. Output Current
OUTPUT DELAY (ns)
250
200
150
T
D
OFF
100
T
D
ON
50
5
7
9
11
13
15
SUPPLY VOLTAGE (V
DD
)
ALL OUTPUTS OFF
0
50
100
TEMPERATURE (°C)
10
8
6
V
DD
= 12V
4
V
DD
= 5V
2
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT CURRENT (A)
Maximum Allowable Duty Cycle, Plastic DIP
V
DD
= 5.0V
Number of Outputs ON
(I
OUT
= 200mA
V
DD
= 5.0V)
8
7
6
5
4
3
2
1
Max. Allowable Duty Cycle at Ambient Temperature of:
25
°
C
85%
97%
100%
100%
100%
100%
100%
100%
40
°
C
72%
82%
96%
100%
100%
100%
100%
100%
50
°
C
64%
73%
85%
100%
100%
100%
100%
100%
60
°
C
55%
63%
73%
88%
100%
100%
100%
100%
70
°
C
46%
53%
62%
75%
93%
100%
100%
100%
V
DD
= 12V
Number of Outputs ON
(I
OUT
= 200mA
V
DD
= 12V)
8
7
6
5
4
3
2
1
Max. Allowable Duty Cycle at Ambient Temperature of:
25
°
C
80%
91%
100%
100%
100%
100%
100%
100%
40
°
C
68%
77%
90%
100%
100%
100%
100%
100%
50
°
C
60%
68%
79%
95%
100%
100%
100%
100%
60
°
C
52%
59%
69%
82%
100%
100%
100%
100%
70
°
C
44%
50%
58%
69%
86%
100%
100%
100%
8-38
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