DRAM MODULE
M372V160(8)0DJ(T)0-C
M372V160(8)0DJ(T)0-C Fast Page Mode
16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung M372V160(8)0DJ(T)0-C is a 16Mx72bits
Dynamic RAM high density memory module. The Samsung
M372V160(8)0DJ(T)0-C consists of eighteen CMOS
16Mx4bits DRAMs in SOJ/TSOP-II 400mil packages and two
16 bits driver IC in TSSOP package mounted on a 168-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor
is mounted on the printed circuit board for each DRAM. The
M372V160(8)0DJ(T)0-C is a Dual In-line Memory Module and
is intended for mounting into 168 pin edge connector sockets.
FEATURES
• Part Identification
Part number
M372V1600DJ0-C
M372V1600DT0-C
M372V1680DJ0-C
M372V1680DT0-C
•
•
•
•
•
•
•
•
PKG
SOJ
TSOP
SOJ
TSOP
8K
4K/64ms
8K/64ms
Ref. CBR Ref.
4K
ROR
4K/64ms
PERFORMANCE RANGE
Speed
-C50
-C60
t
RAC
50ns
60ns
t
CAC
18ns
20ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Fast Page Mode Operation
CAS-before-RAS Refresh capability
RAS-only and Hidden refresh capability
LVTTL compatible inputs and outputs
Single3.3V±0.3V power supply
JEDEC standard pinout & Buffered PDpin
Buffered input except RAS and DQ
PCB : Height(1250mil), double sided component
PIN CONFIGURATIONS
Pin Front Pin Front Pin Front
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
29 *CAS2 57
30 RAS0 58
31
OE0 59
32
V
SS
60
33
A0
61
34
A2
62
35
A4
63
36
A6
64
37
A8
65
38
A10
66
39
A12
67
40
V
CC
68
41 RFU 69
42 RFU 70
43
V
SS
71
44
OE2 72
45 RAS2 73
46 CAS4 74
47 *CAS6 75
48
76
W2
49
V
CC
77
50 RSVD 78
51 RSVD 79
52 DQ18 80
53 DQ19 81
54
V
SS
82
55 DQ20 83
56 DQ21 84
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
RSVD
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
RSVD
V
SS
RSVD
RSVD
V
CC
RFU
*CAS1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
*CAS3
*RAS1
RFU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
RFU
B0
V
SS
RFU
*RAS3
*CAS5
*CAS7
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
RSVD
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
PIN NAMES
Pin Names
A0, B0, A1 - A11
A0, B0, A1 - A12
DQ0 - DQ71
W0, W2
OE0, OE2
RAS0, RAS2
CAS0, CAS4
V
CC
V
SS
NC
PDE
PD1 - 8
ID0 - 1
RSVD
RFU
Function
Address Input(4K ref)
Address Input(8K ref)
Data In/Out
Read/Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power(+3.3V)
Ground
No Connection
Presence Detect Enable
Presence Detect
ID bit
Reserved Use
Reserved for Future Use
Pins marked
′
*
′
are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID0
ID1
50NS
1
1
1
1
0
0
0
0
0
0
60NS
1
1
1
1
0
1
1
0
0
0
NOTE : A12 is used for only M372V1680DJ0/DT0-C (8K Ref.)
PD Note :PD & ID Terminals must each be pulled up through a register to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
ID : 0 for Vss & 1 for N.C
REV. 0.1 Oct. 2000
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0
CAS0
OE0
W0
A0
A1-A11(A12)
U0
M372V160(8)0DJ(T)0-C
RAS2
CAS4
OE2
W2
B0
A1-A11(A12)
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
U9
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
U0-U8
U9-U17
U0-U17
U0-U8
U9-U17
U1
U10
U2
U11
U3
U12
U4
U13
U5
U14
U6
U15
U7
U16
U8
U17
NOTE : A12 is used for only M372V1680DJ0/DT0 (8K Ref.)
Vcc
0.1 or 0.22uF Capacitor
under each DRAM
Vss
To all DRAMs
A0
B0
A1-A11(A12)
W0, OE0
W2, OE2
REV. 0.1 Oct. 2000
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
M372V160(8)0DJ(T)0-C
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
18
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
*2
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Unit
V
V
V
V
*1 : V
CC
+1.3V at pulse width≤15ns, which is measured at V
CC
.
*2 : -1.3V at pulse width≤15ns, which is measured at V
SS
.
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-50
-60
Don′t care
-50
-60
-50
-60
Don′t care
-50
-60
Don′t care
Don′t care
M372V1600DJ(T)0-C
Min
-
-
M372V1680DJ(T)0-C
Min
-
-
-
-
-
-
-
-
-
-10
-5
2.4
-
Max
1440
1260
100
1440
1260
1080
900
30
1980
1800
10
5
-
0.4
Max
1980
1800
100
1980
1800
1080
900
30
1980
1800
10
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-10
-5
2.4
-
I
CC1
* : Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
* : Fast Page Mode Current * (RAS=V
IL
, CAS cycling :
t
PC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I(
IL)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.3V,
all other pins not under test=0 V)
I(
OL)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -2mA)
V
OL
: Output Low Voltage Level (I
OL
= 2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Fast page mode cycle time,
t
PC
.
REV. 0.1 Oct. 2000
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, f = 1MHz)
Item
Input capacitance[A0, B0, A1 - A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0, CAS4]
Input/Output capacitance[DQ0 - 71]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
Min
-
-
-
-
-
M372V160(8)0DJ(T)0-C
Max
20
20
73
20
17
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referencde to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data in set-up time
Data in hold time
Refresh period(4K & 8K)
Write command set-up time
CAS to W delaly time
Column address to W delay time
CAS prechange to W delay time
RAS ro W delay time
Symbol
-50
Min
90
133
50
18
30
5
5
1
30
50
18
48
13
18
13
10
5
8
0
10
30
0
0
-2
10
10
20
13
-2
15
64
0
36
48
53
71
0
40
55
60
83
10K
32
20
10K
18
50
5
5
1
40
60
20
58
15
18
13
10
5
8
0
10
35
0
0
-2
10
10
20
15
-2
15
64
10K
40
25
10K
20
50
Max
Min
110
155
60
20
35
-60
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
7
7
7
7
7,11
9,11
9,11
11
8
8,11
11
4,11
10,11
11
11
11
11
11
3,4,10
3,4,5,11
3,10,11
3,11
6,11
2
Note
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CWD
t
AWD
t
CPWD
t
RWD
REV. 0.1 Oct. 2000
DRAM MODULE
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Parameter
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Fast page mode cycle time
Fast page mode read-modify-write cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Present Detect Read Cycle
PDE to Valid PD bit
PDE to PD bit Inactive
Symbol
-50
Min
10
8
3
40
35
85
10
50
35
15
8
18
18
5
13
18
200K
Max
M372V160(8)0DJ(T)0-C
-60
Min
10
8
3
35
40
76
10
60
40
15
8
20
20
5
15
20
200K
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11
11
11
11
11
Note
11
11
11
3,11
t
CSR
t
CHR
t
RPC
t
CPA
t
PC
t
PRWC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
OEA
t
OED
t
OEZ
t
OEH
t
PD
t
PDOFF
10
2
7
2
10
7
ns
ns
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are V
ih
/V
il
. V
IH
(min) and V
IL
(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
5. Assumes tha
t
RCD
≥
t
RCD
(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
7.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
t
WCS
≥
t
WCS
(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
RWD
≥
t
RWD
(min),
t
CWD
≥
t
CWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in
early write cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
11. The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
REV. 0.1 Oct. 2000