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- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
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© Nexperia B.V. (year). All rights reserved.
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PHKD3NQ10T
Dual N-channel TrenchMOS standard level FET
Rev. 02 — 16 December 2010
Product data sheet
1. Product profile
1.1 General description
Dual standard level N-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
Suitable for use in compact designs
due to low profile
1.3 Applications
DC-to-DC converters
Motor and relay drivers
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
sp
= 25 °C; One MOSFET
conducting
T
sp
= 25 °C
V
GS
= 10 V; I
D
= 1.5 A;
T
j
= 25 °C
V
GS
= 10 V; I
D
= 3 A;
V
DS
= 80 V; T
j
= 25 °C
Min
-
-
-
-
Typ
-
-
-
70
Max Unit
100
3
2
90
V
A
W
mΩ
Static characteristics
Dynamic characteristics
Q
GD
-
8
-
nC
NXP Semiconductors
PHKD3NQ10T
Dual N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S1
G1
S2
G2
D
D
D
D
source1
gate1
source2
gate2
drain2
drain2
drain1
drain1
1
4
S1
G1
S2
G2
mbk725
Simplified outline
8
5
Graphic symbol
D1 D1
D2 D2
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Package
Name
PHKD3NQ10T
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
sp
= 25 °C; both MOSFETs conducting
T
sp
= 70 °C; one MOSFET conducting
T
sp
= 70 °C; both MOSFETs conducting
T
sp
= 25 °C; One MOSFET conducting
I
DM
P
tot
T
stg
T
j
I
S
I
SM
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25 °C
T
sp
= 25 °C; pulsed; t
p
≤
10 s
T
sp
= 25 °C; pulsed; One MOSFET
conducting
T
sp
= 70 °C
T
sp
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≤
150 °C; T
j
≥
25 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-
-
-
-65
-65
-
-
Max
100
100
20
2.2
2.4
1.7
3
12
1.3
2
150
150
2
12
Unit
V
V
V
A
A
A
A
A
W
W
°C
°C
A
A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PHKD3NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
2 of 12
NXP Semiconductors
PHKD3NQ10T
Dual N-channel TrenchMOS standard level FET
100
P
der
(%)
80
003aaf124
100
I
D
(%)
80
003aaf125
60
60
40
40
20
20
0
0
50
100
T
a
(°C)
150
0
0
50
100
T
a
(°C)
150
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature
10
2
I
DM
(A)
10
R
DS(on)
= V
DS
/ I
D
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature
003aaf126
tp = 10
μs
100
μs
1
D.C.
1 ms
10 ms
10
−1
100 ms
10
−2
10
−1
1
10
10
2
V
DS
(V)
10
3
T
mb
= 25 °C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHKD3NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
3 of 12
NXP Semiconductors
PHKD3NQ10T
Dual N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to ambient
Conditions
Surface mounted on FR4 board ; either or
both MOSFETs conducting ; t
≤
10 sec
Surface mounted on FR4 board ; either or
both MOSFETs conducting
Min
-
-
Typ
-
150
Max
62.5
-
Unit
K/W
K/W
10
2
Z
th(j-a)
(K/W)
10
δ
= 0.5
003aaf127
0.2
0.1
0.05
0.02
P
δ
=
t
p
T
1
single pulse
10
−1
t
p
t
T
10
−2
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
t
p
(s)
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHKD3NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
4 of 12
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