®
XC3100A
Logic Cell Array Families
Product Specifications
Features
• Ultra-high-speed FPGA family with six members
– 50-85 MHz system clock rates
– 190 to 325 MHz guaranteed flip-flop toggle rates
– 1.75 to 4.1 ns logic delays
• High-end additional family member in the 22 X 22
CLB array-size XC3195A device
• 8 mA output sink current and 8 mA source current
• Maximum power-down and quiescent current is 5 mA
• Both families are 100% architecture and pin-out
compatible with other XC3000 families
• Beyond this, XC3100A is also software and bitstream
compatible with the XC3000, XC3000A, and XC3000L
families
• 100% PCI complaint (A-2 speed grade in plastic quad
flat pack (PQFP) packaging).
XC3100A combines the features of the XC3000A and
XC3100 families.
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
• More advanced CMOS process
Description
The XC3100A is a performance-optimized relative of the
XC3000 and XC3000A families. While all families are
footprint compatible, XC3100A familiy extends the system
performance beyond 80 MHz.
The XC3100A familiy follows the XC4000 speed-grade
nomenclature, indicating device performance with a num-
ber that is based on the internal logic-block delay, in ns.
The XC3100A family offers the following enhancements
over the popular XC3100 family.
The XC3100A family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more
efficient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3100A devices check the
bitstream format for stop bits in the appropriate positions.
Any error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
outputs are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in all XC3000
families, determined by the individual configuration option.
The XC3100A family is a superset of the XC3000 families.
Any bitstream used to configure an XC3000, XC3000A,
XC3000L or XC3100 device, will configure the same-size
XC3100A device exactly the same way.
Device
XC3120A
XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
CLBs
64
100
144
224
320
484
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
22 x 22
User I/O
Max
64
80
96
120
144
176
Flip-Flops
256
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
28
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,944
2-177
XC3100, XC3100A Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
V
CC
V
IN
V
TS
T
STG
T
SOL
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
Junction temperature plastic
T
J
Junction temperature ceramic
+150
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–65 to +150
+260
+125
Units
V
V
V
°C
°C
°C
°C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed
under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Symbol
V
CC
Description
Supply voltage relative to GND Commercial 0°C to +85°C junction
Supply voltage relative to GND Industrial -40°C to +100°C junction
V
IHT
V
ILT
V
IHC
V
ILC
T
IN
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
High-level input voltage — CMOS configuration
Low-level input voltage — CMOS configuration
Input signal transition time
Min
4.75
4.5
2.0
0
70%
0
Max
5.25
5.5
V
CC
0.8
100%
20%
250
Units
V
V
V
V
V
CC
V
CC
ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°C.
2-178
DC Characteristics Over Operating Conditions
Symbol
V
OH
V
OL
V
OH
V
OL
V
CCPD
I
CCO
Description
High-level output voltage (@ I
OH
= –8.0 mA, V
CC
min)
Commercial
Low-level output voltage (@ I
OL
= 8.0 mA, V
CC
min)
High-level output voltage (@ I
OH
= –8.0 mA, V
CC
min
)
Industrial
Low-level output voltage (@ I
OL
= 8.0 mA, V
CC
min
)
Power-down supply voltage (PWRDWN must be Low)
Quiescent LCA supply current
Chip thresholds programmed as CMOS levels
1
Chip thresholds programmed as TTL levels
I
IL
C
IN
Input Leakage Current
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
I
RIN
I
RLL
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Horizontal long line pull-up (when selected) @ logic Low
0.02
0.20
–10
2.30
0.40
V
V
3.76
0.40
V
V
Min
3.86
Max
Units
V
8
14
+10
mA
mA
µA
10
15
pF
pF
15
20
0.17
2.80
pF
pF
mA
mA
Note: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at V
CC
or GND,
and the LCA configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies
from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package.
2-179
XC3100, XC3100A Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y)
(Combinatorial)
1
CLB Input (A,B,C,D,E)
2
CLB Clock
12 T
CL
4
CLB Input
(Direct In)
6
CLB Input
(Enable Clock)
8
CLB Output
(Flip-Flop)
T
CKO
T
ECCK
7
T
CKEC
T
DICK
11 T
CH
5
T
CKDI
T
ICK
3
T
CKI
T
ILO
CLB Input
(Reset Direct)
13 T
RPW
9 T
RIO
CLB Output
(Flip-Flop)
X5424
T
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
Description
Global and Alternate Clock Distribution*
Either:
Normal
IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast
(CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF
driving a Horizontal Long line (L.L.)*
I to L.L. while T is Low (buffer active) (XC3100)
(XC3100A)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
BIDI
Bidirectional buffer delay
Symbol
-5
Max
-4
Max
-3
Max
-2
Max
-1
ADVANCE INFORMATION
Max
Units
T
PID
T
PIDC
6.8
5.4
6.5
5.1
5.6
4.3
5.2
4.0
4.8
3.8
ns
ns
T
IO
T
IO
T
ON
T
ON
T
PUS
T
PUF
4.1
3.6
5.6
7.1
15.6
12.0
3.7
3.6
5.0
6.5
13.5
10.5
3.1
3.1
4.2
5.7
11.4
8.8
3.1
4.2
5.7
11.4
8.1
2.9
4.0
5.5
10.4
7.1
ns
ns
ns
ns
ns
ns
T
BIDI
1.4
1.2
1.0
0.9
0.85
ns
* Timing is based on the XC3142A, for other devices see XACT timing calculator.
2-180
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Combinatorial Delay
Logic Variables A, B, C, D, E,
to outputs X or Y
Sequential delay
Clock K to outputs X or Y
Clock K to outputs X or Y when Q is returned
through function generators F or G
to drive X or Y
Set-up time before clock K
Logic Variables
Data In
Enable Clock
Reset Direct inactive
Hold Time after clock k
Logic Variables
Data In
Enable Clock
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset, from RESET Pad,
RESET width (Low)
(XC3142A)
delay from RESET pad to outputs X or Y
Notes:
-5
Min
Max Min
-4
Max
-3
Min Max
-2
-1
Units
Symbol
Min Max Min Max
ADVANCE INFORMATION
1 T
ILO
4.1
3.3
2.7
2.2
1.75
1.4
ns
8 T
CKO
3.1
2.5
2.1
1.7
ns
T
QLO
6.3
5.2
4.3
3.5
3.2
ns
A, B, C, D, E
DI
EC
RD
2 T
ICK
3.1
4 T
DICK
2.0
6 T
ECCK
3.8
1.0
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
1.7
1.2
2.3
1.0
ns
ns
ns
ns
A, B, C, D, E
DI
EC
3 T
CKI
0
5 T
CKDI
1.0
7 T
CKEC
1.0
0
1.0
0.8
0
0.9
0.7
0
0.9
0.7
0
0.8
0.6
ns
ns
ns
11 T
CH
12 T
CL
F
CLK
2.4
2.4
190
2.0
2.0
230
1.6
1.6
270
1.3
1.3
325
1.3
1.3
325
ns
ns
MHz
13 T
RPW
9 T
RIO
3.8
4.4
3.2
3.7
2.7
3.1
2.3
2.7
2.3
2.4
ns
ns
T
MRW
14.0
T
MRQ
17.0
14.0
14.0
12.0
12.0
12.0
12.0
12.0
12.0
ns
ns
The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
T
ILO
, T
QLO
and T
ICK
are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increses by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3).
2-181
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